On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <afaer...@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaer...@suse.de>
> ---
> cputlb.c | 4 +--
> exec.c | 7 ++----
> include/exec/exec-all.h | 4 +--
> target-alpha/sys_helper.c | 2 +-
> target-arm/helper.c | 8 ++++--
> target-cris/mmu.c | 3 ++-
> target-cris/op_helper.c | 12 ++++++---
> target-i386/misc_helper.c | 4 ++-
> target-i386/svm_helper.c | 3 ++-
> target-microblaze/mmu.c | 3 ++-
> target-mips/helper.c | 8 ++++--
> target-openrisc/sys_helper.c | 4 +--
> target-ppc/mmu_helper.c | 58
> +++++++++++++++++++++++++-------------------
> target-s390x/mem_helper.c | 7 +++---
> target-s390x/misc_helper.c | 6 +++--
> target-sh4/helper.c | 19 +++++++++------
> target-sparc/ldst_helper.c | 7 ++++--
> target-xtensa/op_helper.c | 11 ++++++---
> 18 files changed, 103 insertions(+), 67 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index 20a1efe..817180e 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -91,9 +91,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry,
> target_ulong addr)
> }
> }
>
> -void tlb_flush_page(CPUArchState *env, target_ulong addr)
> +void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> - CPUState *cpu = ENV_GET_CPU(env);
> + CPUArchState *env = cpu->env_ptr;
> int i;
> int mmu_idx;
>
> diff --git a/exec.c b/exec.c
> index 16e3c4d..9210834 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -433,7 +433,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr,
> vaddr len,
> int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
> int flags, CPUWatchpoint **watchpoint)
> {
> - CPUArchState *env = cpu->env_ptr;
> vaddr len_mask = ~(len - 1);
> CPUWatchpoint *wp;
>
> @@ -457,7 +456,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr,
> vaddr len,
> QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
> }
>
> - tlb_flush_page(env, addr);
> + tlb_flush_page(cpu, addr);
>
> if (watchpoint)
> *watchpoint = wp;
> @@ -484,11 +483,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
> vaddr len,
> /* Remove a specific watchpoint by reference. */
> void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
> {
> - CPUArchState *env = cpu->env_ptr;
> -
> QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
>
> - tlb_flush_page(env, watchpoint->vaddr);
> + tlb_flush_page(cpu, watchpoint->vaddr);
>
> g_free(watchpoint);
> }
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 847ed84..550e58d 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -96,14 +96,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start,
> tb_page_addr_t end,
> int is_cpu_write_access);
> #if !defined(CONFIG_USER_ONLY)
> /* cputlb.c */
> -void tlb_flush_page(CPUArchState *env, target_ulong addr);
> +void tlb_flush_page(CPUState *cpu, target_ulong addr);
> void tlb_flush(CPUArchState *env, int flush_global);
> void tlb_set_page(CPUState *cpu, target_ulong vaddr,
> hwaddr paddr, int prot,
> int mmu_idx, target_ulong size);
> void tb_invalidate_phys_addr(hwaddr addr);
> #else
> -static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
> +static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> }
>
> diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
> index 035810c..5f7d7dd 100644
> --- a/target-alpha/sys_helper.c
> +++ b/target-alpha/sys_helper.c
> @@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env)
>
> void helper_tbis(CPUAlphaState *env, uint64_t p)
> {
> - tlb_flush_page(env, p);
> + tlb_flush_page(CPU(alpha_env_get_cpu(env)), p);
> }
>
> void helper_tb_flush(CPUAlphaState *env)
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 34407a1..4daf82e 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -311,8 +311,10 @@ static int tlbiall_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
> - tlb_flush_page(env, value & TARGET_PAGE_MASK);
> + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
> return 0;
> }
>
> @@ -327,8 +329,10 @@ static int tlbiasid_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
> - tlb_flush_page(env, value & TARGET_PAGE_MASK);
> + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
> return 0;
> }
>
> diff --git a/target-cris/mmu.c b/target-cris/mmu.c
> index 512e28b..1c95a41 100644
> --- a/target-cris/mmu.c
> +++ b/target-cris/mmu.c
> @@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result
> *res,
>
> void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> {
> + CRISCPU *cpu = cris_env_get_cpu(env);
> target_ulong vaddr;
> unsigned int idx;
> uint32_t lo, hi;
> @@ -315,7 +316,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> vaddr = tlb_vpn << TARGET_PAGE_BITS;
> D_LOG("flush pid=%x vaddr=%x\n",
> pid, vaddr);
> - tlb_flush_page(env, vaddr);
> + tlb_flush_page(CPU(cpu), vaddr);
> }
> }
> }
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index d28bd61..bd9a583 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -98,8 +98,11 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> {
> #if !defined(CONFIG_USER_ONLY)
> - tlb_flush_page(env, env->pregs[PR_SPC]);
> - tlb_flush_page(env, new_spc);
> + CRISCPU *cpu = cris_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> +
> + tlb_flush_page(cs, env->pregs[PR_SPC]);
> + tlb_flush_page(cs, new_spc);
> #endif
> }
>
> @@ -114,6 +117,9 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
>
> void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> {
> +#if !defined(CONFIG_USER_ONLY)
> + CRISCPU *cpu = cris_env_get_cpu(env);
> +#endif
> uint32_t srs;
> srs = env->pregs[PR_SRS];
> srs &= 3;
> @@ -155,7 +161,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t
> sreg, uint32_t reg)
> D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
> vaddr, tlb_v, env->pc);
> if (tlb_v) {
> - tlb_flush_page(env, vaddr);
> + tlb_flush_page(CPU(cpu), vaddr);
> }
> }
> }
> diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
> index 4b7a142..64dceca 100644
> --- a/target-i386/misc_helper.c
> +++ b/target-i386/misc_helper.c
> @@ -221,8 +221,10 @@ void helper_lmsw(CPUX86State *env, target_ulong t0)
>
> void helper_invlpg(CPUX86State *env, target_ulong addr)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> +
> cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
> - tlb_flush_page(env, addr);
> + tlb_flush_page(CPU(cpu), addr);
> }
>
> void helper_rdtsc(CPUX86State *env)
> diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
> index fbf8359..197269b 100644
> --- a/target-i386/svm_helper.c
> +++ b/target-i386/svm_helper.c
> @@ -435,6 +435,7 @@ void helper_skinit(CPUX86State *env)
>
> void helper_invlpga(CPUX86State *env, int aflag)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> target_ulong addr;
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0);
> @@ -447,7 +448,7 @@ void helper_invlpga(CPUX86State *env, int aflag)
>
> /* XXX: could use the ASID to see if it is needed to do the
> flush */
> - tlb_flush_page(env, addr);
> + tlb_flush_page(CPU(cpu), addr);
> }
>
> void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
> diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
> index 9182934..5b768f2 100644
> --- a/target-microblaze/mmu.c
> +++ b/target-microblaze/mmu.c
> @@ -34,6 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f)
>
> static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
> {
> + CPUState *cs = CPU(mb_env_get_cpu(env));
> struct microblaze_mmu *mmu = &env->mmu;
> unsigned int tlb_size;
> uint32_t tlb_tag, end, t;
> @@ -47,7 +48,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
> end = tlb_tag + tlb_size;
>
> while (tlb_tag < end) {
> - tlb_flush_page(env, tlb_tag);
> + tlb_flush_page(cs, tlb_tag);
> tlb_tag += TARGET_PAGE_SIZE;
> }
> }
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index ca2f0e7..b28ae9b 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -653,6 +653,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
> #if !defined(CONFIG_USER_ONLY)
> void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> + CPUState *cs;
> r4k_tlb_t *tlb;
> target_ulong addr;
> target_ulong end;
> @@ -678,6 +680,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int
> use_extra)
> /* 1k pages are not supported. */
> mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
> if (tlb->V0) {
> + cs = CPU(cpu);
> addr = tlb->VPN & ~mask;
> #if defined(TARGET_MIPS64)
> if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
> @@ -686,11 +689,12 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx,
> int use_extra)
> #endif
> end = addr | (mask >> 1);
> while (addr < end) {
> - tlb_flush_page (env, addr);
> + tlb_flush_page(cs, addr);
> addr += TARGET_PAGE_SIZE;
> }
> }
> if (tlb->V1) {
> + cs = CPU(cpu);
> addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
> #if defined(TARGET_MIPS64)
> if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
> @@ -699,7 +703,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int
> use_extra)
> #endif
> end = addr | mask;
> while (addr - 1 < end) {
> - tlb_flush_page (env, addr);
> + tlb_flush_page(cs, addr);
> addr += TARGET_PAGE_SIZE;
> }
> }
> diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
> index cccbc0e..8f07f78 100644
> --- a/target-openrisc/sys_helper.c
> +++ b/target-openrisc/sys_helper.c
> @@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
> case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
> idx = spr - TO_SPR(1, 512);
> if (!(rb & 1)) {
> - tlb_flush_page(env, env->tlb->dtlb[0][idx].mr &
> TARGET_PAGE_MASK);
> + tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
> }
> env->tlb->dtlb[0][idx].mr = rb;
> break;
> @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
> case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
> idx = spr - TO_SPR(2, 512);
> if (!(rb & 1)) {
> - tlb_flush_page(env, env->tlb->itlb[0][idx].mr &
> TARGET_PAGE_MASK);
> + tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
> }
> env->tlb->itlb[0][idx].mr = rb;
> break;
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index f4dac00..cf652b7 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -252,6 +252,7 @@ static inline void
> ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> int is_code, int match_epn)
> {
> #if !defined(FLUSH_ALL_TLBS)
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> ppc6xx_tlb_t *tlb;
> int way, nr;
>
> @@ -263,7 +264,7 @@ static inline void
> ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
> env->nb_tlb, eaddr);
> pte_invalidate(&tlb->pte0);
> - tlb_flush_page(env, tlb->EPN);
> + tlb_flush_page(cs, tlb->EPN);
> }
> }
> #else
> @@ -657,6 +658,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState
> *env,
> target_ulong eaddr, uint32_t
> pid)
> {
> #if !defined(FLUSH_ALL_TLBS)
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> ppcemb_tlb_t *tlb;
> hwaddr raddr;
> target_ulong page, end;
> @@ -667,7 +669,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState
> *env,
> if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
> end = tlb->EPN + tlb->size;
> for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> tlb->prot &= ~PAGE_VALID;
> break;
> @@ -1727,6 +1729,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
> target_ulong address,
> static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
> target_ulong mask)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> target_ulong base, end, page;
>
> base = BATu & ~0x0001FFFF;
> @@ -1734,7 +1737,7 @@ static inline void do_invalidate_BAT(CPUPPCState *env,
> target_ulong BATu,
> LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
> TARGET_FMT_lx ")\n", base, end, mask);
> for (page = base; page != end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> LOG_BATS("Flush done\n");
> }
> @@ -1941,6 +1944,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
> target_ulong addr)
> {
> #if !defined(FLUSH_ALL_TLBS)
> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + CPUState *cs;
>
> addr &= TARGET_PAGE_MASK;
> switch (env->mmu_model) {
> @@ -1974,25 +1978,26 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
> target_ulong addr)
> case POWERPC_MMU_601:
> /* tlbie invalidate TLBs for all segments */
> addr &= ~((target_ulong)-1ULL << 28);
> + cs = CPU(cpu);
> /* XXX: this case should be optimized,
> * giving a mask to tlb_flush_page
> */
> - tlb_flush_page(env, addr | (0x0 << 28));
> - tlb_flush_page(env, addr | (0x1 << 28));
> - tlb_flush_page(env, addr | (0x2 << 28));
> - tlb_flush_page(env, addr | (0x3 << 28));
> - tlb_flush_page(env, addr | (0x4 << 28));
> - tlb_flush_page(env, addr | (0x5 << 28));
> - tlb_flush_page(env, addr | (0x6 << 28));
> - tlb_flush_page(env, addr | (0x7 << 28));
> - tlb_flush_page(env, addr | (0x8 << 28));
> - tlb_flush_page(env, addr | (0x9 << 28));
> - tlb_flush_page(env, addr | (0xA << 28));
> - tlb_flush_page(env, addr | (0xB << 28));
> - tlb_flush_page(env, addr | (0xC << 28));
> - tlb_flush_page(env, addr | (0xD << 28));
> - tlb_flush_page(env, addr | (0xE << 28));
> - tlb_flush_page(env, addr | (0xF << 28));
> + tlb_flush_page(cs, addr | (0x0 << 28));
> + tlb_flush_page(cs, addr | (0x1 << 28));
> + tlb_flush_page(cs, addr | (0x2 << 28));
> + tlb_flush_page(cs, addr | (0x3 << 28));
> + tlb_flush_page(cs, addr | (0x4 << 28));
> + tlb_flush_page(cs, addr | (0x5 << 28));
> + tlb_flush_page(cs, addr | (0x6 << 28));
> + tlb_flush_page(cs, addr | (0x7 << 28));
> + tlb_flush_page(cs, addr | (0x8 << 28));
> + tlb_flush_page(cs, addr | (0x9 << 28));
> + tlb_flush_page(cs, addr | (0xA << 28));
> + tlb_flush_page(cs, addr | (0xB << 28));
> + tlb_flush_page(cs, addr | (0xC << 28));
> + tlb_flush_page(cs, addr | (0xD << 28));
> + tlb_flush_page(cs, addr | (0xE << 28));
> + tlb_flush_page(cs, addr | (0xF << 28));
> break;
> #if defined(TARGET_PPC64)
> case POWERPC_MMU_64B:
> @@ -2324,6 +2329,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
> entry,
> target_ulong val)
> {
> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> ppcemb_tlb_t *tlb;
> target_ulong page, end;
>
> @@ -2337,7 +2343,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
> entry,
> LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
> TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
> for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> }
> tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT)
> @@ -2347,7 +2353,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
> entry,
> * of the ppc or ppc64 one
> */
> if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
> - cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u "
> + cpu_abort(cs, "TLB size " TARGET_FMT_lu " < %u "
> "are not supported (%d)\n",
> tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
> }
> @@ -2356,7 +2362,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
> entry,
> tlb->prot |= PAGE_VALID;
> if (val & PPC4XX_TLBHI_E) {
> /* XXX: TO BE FIXED */
> - cpu_abort(CPU(cpu),
> + cpu_abort(cs,
> "Little-endian TLB entries are not supported by
> now\n");
> }
> } else {
> @@ -2376,7 +2382,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
> entry,
> LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
> TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
> for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> }
> }
> @@ -2665,7 +2671,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
> }
>
> if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, tlb->mas2 & MAS2_EPN_MASK);
> + tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
> } else {
> tlb_flush(env, 1);
> }
> @@ -2774,6 +2780,8 @@ static inline void
> booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn,
>
> void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> if (address & 0x4) {
> /* flush all entries */
> if (address & 0x8) {
> @@ -2793,7 +2801,7 @@ void helper_booke206_tlbivax(CPUPPCState *env,
> target_ulong address)
> } else {
> /* flush TLB0 entries */
> booke206_invalidate_ea_tlb(env, 0, address);
> - tlb_flush_page(env, address & MAS2_EPN_MASK);
> + tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK);
> }
> }
>
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index cd84337..6bff6cc 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -1012,6 +1012,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l,
> uint64_t a1, uint64_t a2)
> /* invalidate pte */
> void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
> {
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> uint64_t page = vaddr & TARGET_PAGE_MASK;
> uint64_t pte = 0;
>
> @@ -1025,13 +1026,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t
> pte_addr, uint64_t vaddr)
>
> /* XXX we exploit the fact that Linux passes the exact virtual
> address here - it's not obliged to! */
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
>
> /* XXX 31-bit hack */
> if (page & 0x80000000) {
> - tlb_flush_page(env, page & ~0x80000000);
> + tlb_flush_page(cs, page & ~0x80000000);
> } else {
> - tlb_flush_page(env, page | 0x80000000);
> + tlb_flush_page(cs, page | 0x80000000);
> }
> }
>
> diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
> index 54e6d36..d638955 100644
> --- a/target-s390x/misc_helper.c
> +++ b/target-s390x/misc_helper.c
> @@ -290,11 +290,13 @@ uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num,
> uint64_t mem,
> /* Set Prefix */
> void HELPER(spx)(CPUS390XState *env, uint64_t a1)
> {
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> uint32_t prefix = a1 & 0x7fffe000;
> +
> env->psa = prefix;
> qemu_log("prefix: %#x\n", prefix);
> - tlb_flush_page(env, 0);
> - tlb_flush_page(env, TARGET_PAGE_SIZE);
> + tlb_flush_page(cs, 0);
> + tlb_flush_page(cs, TARGET_PAGE_SIZE);
> }
>
> static inline uint64_t clock_value(CPUS390XState *env)
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 7add92d..c56e543 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -304,7 +304,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int
> utlb)
> itlb = itlb_replacement(env);
> ientry = &env->itlb[itlb];
> if (ientry->v) {
> - tlb_flush_page(env, ientry->vpn << 10);
> + tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
> }
> *ientry = env->utlb[utlb];
> update_itlb_use(env, itlb);
> @@ -535,7 +535,7 @@ void cpu_load_tlb(CPUSH4State * env)
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(env, address);
> + tlb_flush_page(CPU(cpu), address);
> }
>
> /* Take values into cpu status from registers. */
> @@ -611,7 +611,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s,
> hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in itlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> }
> entry->asid = asid;
> entry->vpn = vpn;
> @@ -653,7 +653,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s,
> hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> }
> entry->ppn = (mem_value & 0x1ffffc00) >> 10;
> entry->v = (mem_value & 0x00000100) >> 8;
> @@ -737,16 +737,19 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s,
> hwaddr addr,
> }
> }
>
> - if (needs_tlb_flush)
> - tlb_flush_page(s, vpn << 10);
> + if (needs_tlb_flush) {
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
> + }
>
> } else {
> int index = (addr & 0x00003f00) >> 8;
> tlb_t * entry = &s->utlb[index];
> if (entry->v) {
> + CPUState *cs = CPU(sh_env_get_cpu(s));
> +
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(cs, address);
> }
> entry->asid = asid;
> entry->vpn = vpn;
> @@ -797,7 +800,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s,
> hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> }
> entry->ppn = (mem_value & 0x1ffffc00) >> 10;
> entry->v = (mem_value & 0x00000100) >> 8;
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index b222dff..44c54f1 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -141,6 +141,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,
>
> /* flush page range if translation is valid */
> if (TTE_IS_VALID(tlb->tte)) {
> + CPUState *cs = CPU(sparc_env_get_cpu(env1));
>
> mask = 0xffffffffffffe000ULL;
> mask <<= 3 * ((tlb->tte >> 61) & 3);
> @@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,
> va = tlb->tag & mask;
>
> for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env1, va + offset);
> + tlb_flush_page(cs, va + offset);
> }
> }
>
> @@ -715,6 +716,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong
> addr, int asi, int size,
> void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int
> asi,
> int size)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> +
> helper_check_align(env, addr, size - 1);
> switch (asi) {
> case 2: /* SuperSparc MXCC registers and Leon3 cache control */
> @@ -856,7 +859,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr,
> uint64_t val, int asi,
> DPRINTF_MMU("mmu flush level %d\n", mmulev);
> switch (mmulev) {
> case 0: /* flush page */
> - tlb_flush_page(env, addr & 0xfffff000);
> + tlb_flush_page(CPU(cpu), addr & 0xfffff000);
> break;
> case 1: /* flush segment (256k) */
> case 2: /* flush region (16M) */
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 5952ed8..5771841 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -679,7 +679,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v,
> uint32_t dtlb)
> uint32_t wi;
> xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
> if (entry->variable && entry->asid) {
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
> entry->asid = 0;
> }
> }
> @@ -724,21 +724,24 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
> void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
> unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
> {
> + XtensaCPU *cpu = xtensa_env_get_cpu(env);
> + CPUState *cs;
> xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
>
> if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
> if (entry->variable) {
> + cs = CPU(cpu);
> if (entry->asid) {
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(cs, entry->vaddr);
> }
> xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(cs, entry->vaddr);
> } else {
> qemu_log("%s %d, %d, %d trying to set immutable entry\n",
> __func__, dtlb, wi, ei);
> }
> } else {
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(CPU(cpu), entry->vaddr);
> if (xtensa_option_enabled(env->config,
> XTENSA_OPTION_REGION_TRANSLATION)) {
> entry->paddr = pte & REGION_PAGE_MASK;
target-openrisc: Tested-by: Jia Liu <pro...@gmail.com>
> --
> 1.8.1.4
>
