Signed-off-by: Andreas Färber <afaer...@suse.de>
---
cputlb.c | 4 ++--
include/exec/exec-all.h | 2 +-
target-alpha/helper.c | 2 +-
target-arm/helper.c | 2 +-
target-cris/helper.c | 2 +-
target-i386/helper.c | 2 +-
target-lm32/helper.c | 6 +++---
target-m68k/helper.c | 3 +--
target-microblaze/helper.c | 4 ++--
target-mips/helper.c | 2 +-
target-moxie/helper.c | 2 +-
target-openrisc/mmu.c | 2 +-
target-ppc/mmu-hash32.c | 8 ++++----
target-ppc/mmu-hash64.c | 4 ++--
target-ppc/mmu_helper.c | 2 +-
target-s390x/helper.c | 2 +-
target-sh4/helper.c | 2 +-
target-sparc/mmu_helper.c | 6 +++---
target-unicore32/softmmu.c | 2 +-
target-xtensa/op_helper.c | 8 ++++----
20 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index ddcd2cd..f8b9566 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -236,11 +236,11 @@ static void tlb_add_large_page(CPUState *cpu,
target_ulong vaddr,
/* Add a new TLB entry. At most one entry for a given virtual address
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
MemoryRegionSection *section;
unsigned int index;
target_ulong address;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 1838ae1..847ed84 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -98,7 +98,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start,
tb_page_addr_t end,
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(hwaddr addr);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index f0ba5dd..fd4a70c 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -344,7 +344,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
int rw,
return 1;
}
- tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
+ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index bc00858..06dd57c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3040,7 +3040,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
/* Map a single [sub]page. */
phys_addr &= ~(hwaddr)0x3ff;
address &= ~(uint32_t)0x3ff;
- tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 3c4501c..08b3864 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
*/
phy = res.phy & ~0x80000000;
prot = res.prot;
- tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index a6d64a6..e0df092 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -864,7 +864,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
paddr = (pte & TARGET_PAGE_MASK) + page_offset;
vaddr = virt_addr + page_offset;
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
do_fault_protect:
error_code = PG_ERROR_P_MASK;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index b2093a8..daf0f2f 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
address &= TARGET_PAGE_MASK;
prot = PAGE_BITS;
if (env->flags & LM32_FLAG_IGNORE_MSB) {
- tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
- TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
+ TARGET_PAGE_SIZE);
} else {
- tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
}
return 0;
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index e38065c..219e8b3 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -300,12 +300,11 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- M68kCPU *cpu = M68K_CPU(cs);
int prot;
address &= TARGET_PAGE_MASK;
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 4825415..50aa55a 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -77,7 +77,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int
rw,
DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
mmu_idx, vaddr, paddr, lu.prot));
- tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx,
TARGET_PAGE_SIZE);
+ tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
} else {
env->sregs[SR_EAR] = address;
@@ -108,7 +108,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
/* MMU disabled or not available. */
address &= TARGET_PAGE_MASK;
prot = PAGE_BITS;
- tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
return r;
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 698c3d1..ca2f0e7 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -300,7 +300,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
" prot %d\n",
__func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 04b36b7..3d0c34d 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -148,7 +148,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
phy = res.phy;
r = 0;
}
- tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
return r;
}
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index b1830da..cc026a7 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -194,7 +194,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs,
address, rw);
if (ret == TLBRET_MATCH) {
- tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 6a4d6a8..1cc1916 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -400,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr, int rwx,
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
/* Translation is off */
raddr = eaddr;
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -427,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr, int rwx,
return 1;
}
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -441,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr, int rwx,
if (sr & SR32_T) {
if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
&raddr, &prot) == 0) {
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -522,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr, int rwx,
raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 82bfa7c..b060e69 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -416,7 +416,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr,
/* Translation is off */
/* In real mode the top 4 effective address bits are ignored */
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -517,7 +517,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,
target_ulong eaddr,
raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 5a237ce..ff70b38 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1506,7 +1506,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
target_ulong address,
}
ret = get_physical_address(env, &ctx, address, rw, access_type);
if (ret == 0) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index e1ed6c0..207af52 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -411,7 +411,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr
orig_vaddr,
DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
(uint64_t)vaddr, (uint64_t)raddr, prot);
- tlb_set_page(env, orig_vaddr, raddr, prot,
+ tlb_set_page(cs, orig_vaddr, raddr, prot,
mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 0357ceb..b444da1 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -506,7 +506,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr
address, int rw,
address &= TARGET_PAGE_MASK;
physical &= TARGET_PAGE_MASK;
- tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index ea72657..ad070de 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -216,7 +216,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
TARGET_FMT_lx "\n", address, paddr, vaddr);
#endif
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
}
@@ -232,7 +232,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
neverland. Fake/overridden mappings will be flushed when
switching to normal mode. */
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
} else {
if (rw & 2) {
@@ -727,7 +727,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw,
env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context);
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
}
/* XXX */
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 2e26fd1..d0527e5 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -249,7 +249,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
/* Map a single page. */
phys_addr &= TARGET_PAGE_MASK;
address &= TARGET_PAGE_MASK;
- tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 164b34b..5952ed8 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -74,10 +74,10 @@ void tlb_fill(CPUState *cs,
vaddr, is_write, mmu_idx, paddr, ret);
if (ret == 0) {
- tlb_set_page(env,
- vaddr & TARGET_PAGE_MASK,
- paddr & TARGET_PAGE_MASK,
- access, mmu_idx, page_size);
+ tlb_set_page(cs,
+ vaddr & TARGET_PAGE_MASK,
+ paddr & TARGET_PAGE_MASK,
+ access, mmu_idx, page_size);
} else {
cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
--
1.8.1.4
