-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Il 09/07/2013 09:17, David Gibson ha scritto: > So, Alexey addressed the xics vs. xics-kvm issues. But there's > another factor here. It's not clear to me how you'd QOM this > component. > > What's being registered here is the "presentation server". That's > the per-CPU part - vaguely equivalent to the LAPIC on x86. x86 > doesn't have something equivalent here, because they register the > LAPIC state as part of the CPU state, but we can't do that because > the ICP is not bound to the CPU as tightly - a POWER7 using a > different interrupt architecture would certainly be possible.
That's also possible with x86, in fact there is a command line option to only use the legacy 8259 interrupt controller. The LAPIC is a separate device from the CPU, it just happens that the CPU also needs a back-pointer to the LAPIC. If you do not need that back-pointer, just do not put it in. The ICP can still have a link property that points to the CPU. Paolo > So to do this with QOM, would the ICP need to be registered as a > child of the cpu object? -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJR4/StAAoJEBvWZb6bTYbyxmQQAJi8B6Dlyrg/6EKwtK834MQ/ +XWQda+EfYVzFgECIxzQtiumUMNv2pxOEJ1Ij1jgs4o+n18mH14moO1A1r2YAONx 8eXpmxwd3vt0ka/fiW7BP4mDThUT8u0EYhyLkRnMkXfw2RTElw/E+Cx5v2aCK43C bz1Ws7Dtjsw3pDinobrl32NhwiJZ+SQvEGnxZiMt1R3PFu7m5cuBdr7Cmc6ZWFAq lvnUXNqOaAI8sywcsXLMFTan9rzdz0eNRxpMBB9F60szRFmTIGDv8kww0LLwJE1/ pTXv0Ts7jwdA0wykIQQKFLtmLKJGfuq8U4qe/uH+AnevC0CZ0A3/g3y+juC8qKnA 8vUPZdwUy+J4NqdZM1wMMd2QOA1XO4Pd6RTHY5kU7ITDma5A/sHsrysz8XfrcL4T X8sEDCoUprMn/qF+52671Ol4T8mT5N0pwkjak5yjtQbcmAk4uSXMCS+eAbQ2i8ae 2KCLuCAFTuDIon52UtqEcV/7QHUVp1vB8qjhZjqkLpEgrR7ojINCmUpNaxLddOmz b3v64JOYk4QNEJ0yccFSSib7LwIxYqilx0Pyk0pl5f5G+eqMFlJhxFSS26QxxIqR fJMObjZxdoCeH49TLOshRUKJpRi1f7ChxlREiY0xC2eMF0k3fDEWCHqg4K5vMidd eloFvLkkygN52W9C8f1E =NpYW -----END PGP SIGNATURE-----
