On Sat, Apr 13, 2013 at 02:20:10PM +0100, Peter Maydell wrote: > On 13 April 2013 13:47, Aurelien Jarno <aurel...@aurel32.net> wrote: > > fabs, fnabs and fneg are just flipping the bit sign of an FP register, > > this can be implemented in TCG instead of using softfloat. > > + tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], > > + ~(1LL << 63)); > > "1LL << 63" is undefined behaviour; you probably want "1ULL << 63". >
Thanks, I'll fix that in the next version. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurel...@aurel32.net http://www.aurel32.net
