On 13 April 2013 13:47, Aurelien Jarno <aurel...@aurel32.net> wrote: > fabs, fnabs and fneg are just flipping the bit sign of an FP register, > this can be implemented in TCG instead of using softfloat. > + tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], > + ~(1LL << 63));
"1LL << 63" is undefined behaviour; you probably want "1ULL << 63". -- PMM
