On Sat, Apr 6, 2013 at 5:01 AM, Peter Maydell <peter.mayd...@linaro.org> wrote:
> On 3 April 2013 05:33, Peter Crosthwaite <peter.crosthwa...@xilinx.com> wrote:
>> The LQSPI bus attachment supports byte/halfword and misaligned
>> accesses. Fixed. Refactored the LQSPI cache to be byte-wise
>> instead of word wise accordingly.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
>> ---
>>
>> hw/xilinx_spips.c | 31 +++++++++++++++++--------------
>> 1 files changed, 17 insertions(+), 14 deletions(-)
>>
>> diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
>> index 32d8db8..cb45a9c 100644
>> --- a/hw/xilinx_spips.c
>> +++ b/hw/xilinx_spips.c
>> @@ -160,7 +160,7 @@ typedef struct {
>> typedef struct {
>> XilinxSPIPS parent_obj;
>>
>> - uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
>> + uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
>
> Is it really right that this buffer isn't in the vmstate,
> by the way?
>
Yes,
Its a software transparent cache. The cache is lost on migration. Post
load the first access just refreshes the cache and the guest is none
the wiser.
Regards.
{eter
>> hwaddr lqspi_cached_addr;
>> } XilinxQSPIPS;
>
> -- PMM
>
