On Feb 29, 2008, at 10:41 AM, Bernhard Kauer wrote:
On Wed, Feb 27, 2008 at 06:03:49PM +0100, Alexander Graf wrote:
MSR_EFER_SVM is not defined in my qemu version. What does the bit
change
if set?
The AMD vol2 reads like this:
Secure Virtual Machine Enable (SVME) Bit. Bit 12. Enables the SVM
extensions.
When this bit is zero, the SVM instructions cause #UD exceptions.
The bit was called MSR_EFER_SVME_MASK in svm.h before, I renamed it
in the
attached patch to MSR_EFER_SVME to match the style of the other
definitions
in cpu.h.
BTW, triggering the above mentioned #UD is missing in the code...
Could you please add the #UD check to the vm* helpers too? It's not
that many and I don't see a point in implementing this half-heartedly.
Keep in mind that updating the bit should fail within a virtual machine.
Alex
