On Wed, Feb 27, 2008 at 06:03:49PM +0100, Alexander Graf wrote:
> MSR_EFER_SVM is not defined in my qemu version. What does the bit change
> if set?
The AMD vol2 reads like this:
Secure Virtual Machine Enable (SVME) Bit. Bit 12. Enables the SVM
extensions.
When this bit is zero, the SVM instructions cause #UD exceptions.
The bit was called MSR_EFER_SVME_MASK in svm.h before, I renamed it in the
attached patch to MSR_EFER_SVME to match the style of the other definitions
in cpu.h.
BTW, triggering the above mentioned #UD is missing in the code...
Bernhard Kauer
Index: target-i386/helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-i386/helper.c,v
retrieving revision 1.101
diff -u -r1.101 helper.c
--- target-i386/helper.c 3 Feb 2008 03:26:30 -0000 1.101
+++ target-i386/helper.c 29 Feb 2008 09:33:41 -0000
@@ -2802,6 +2802,8 @@
update_mask |= MSR_EFER_FFXSR;
if (env->cpuid_ext2_features & CPUID_EXT2_NX)
update_mask |= MSR_EFER_NXE;
+ if (env->cpuid_ext3_features & CPUID_EXT3_SVM)
+ update_mask |= MSR_EFER_SVME;
env->efer = (env->efer & ~update_mask) |
(val & update_mask);
}
Index: target-i386/svm.h
===================================================================
RCS file: /sources/qemu/qemu/target-i386/svm.h,v
retrieving revision 1.1
diff -u -r1.1 svm.h
--- target-i386/svm.h 23 Sep 2007 15:30:28 -0000 1.1
+++ target-i386/svm.h 29 Feb 2008 09:33:41 -0000
@@ -179,7 +179,7 @@
#define SVM_CPUID_FEATURE_SHIFT 2
#define SVM_CPUID_FUNC 0x8000000a
-#define MSR_EFER_SVME_MASK (1ULL << 12)
+#define MSR_EFER_SVME (1ULL << 12)
#define SVM_SELECTOR_S_SHIFT 4
#define SVM_SELECTOR_DPL_SHIFT 5
