On 01/29/2013 07:02 PM, Scott Wood wrote:
On 01/29/2013 07:52:58 AM, Alexander Graf wrote:
The bit that makes a dcbz instruction a dcbzl instruction was
declared as
reserved in ppc32 ISAs. However, hardware simply ignores the bit, making
code valid if it simply invokes dcbzl instead of dcbz even on 750 and
G4.
Thus, mark the bit as unreserved so that we properly emulate a simple
dcbz
in case we're running on non-G5s.
FWIW, dcbzl exists on e500mc, which is 32-bit. If we ever support
L1CSR0[DCBZ32] on e500mc, we'll need proper dcbzl support rather than
just a dcbz alias.
Then the e500 machine wouldn't set PPC_CACHE_DCBZ, but a special
PPC_CACHE_E500MC. Just like 970 sets PPC_CACHE_DCBZT instead today.
Unless of course we can somehow get to the cpu class from env. Then we
could also ask for the machine type and implement dcbzl accordingly.
Alex
