The bit that makes a dcbz instruction a dcbzl instruction was declared as reserved in ppc32 ISAs. However, hardware simply ignores the bit, making code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.
Thus, mark the bit as unreserved so that we properly emulate a simple dcbz in case we're running on non-G5s. Reported-by: Amadeusz Sławiński <am...@asmblr.net> Signed-off-by: Alexander Graf <ag...@suse.de> --- target-ppc/translate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 798b7ac..9b98493 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8648,7 +8648,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), -GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), +GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), -- 1.6.0.2
