Blue Swirl <blauwir...@gmail.com> writes: MULX implies a bunch of other instructions due to CPUID flag grouping. ADCX and ADOX can be implemented separately. None of these and the other instructions in the MULX group look very complex. I had not realised that qemu disabled instructions when emulating a CPU not supposed to support them.
The other extensions like 256 bit float and extending existing SSE instructions to use them would need much more work. FMA looks simple except for the YMM variants. Random number instructions increase demand of cryptographically secure random number supply from the host. I strongly doubt that cryptographically secure random numbers can in general be supplied by qemu. I would strongly suggest that these instructions are not enabled by default, not to cause unintensional abuse of them. Some scary flag could enable them, perhaps "--enable-supposedly-cryptographically-secure-random-number-instructions-in-an-unsafe-manner". :-) Of course, if the host claims to have such random instructions, executing these and passing on the result makes some sense. I don't think cryptographers trust these instructions anyway. They might very well be generated with a PRNG, and nobody could tell. http://dilbert.com/strips/comic/2001-10-25/ There is no public silicon yet. Haswell release is supposedly going to happen on June 2. Broadwell (with ADCX and ADOX) will not happen until perhaps 2015. -- Torbjörn
