The device return false from the can receive function when the FIFO is
full. This mean the device should check for buffered input whenever a byte is
popped from the FIFO.

Reported-by: Jason Wu <hua...@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---
 hw/cadence_uart.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index 686e617..a6196a2 100644
--- a/hw/cadence_uart.c
+++ b/hw/cadence_uart.c
@@ -343,6 +343,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
         if (!s->rx_count) {
             s->r[R_SR] |= UART_SR_INTR_REMPTY;
         }
+        qemu_chr_accept_input(s->chr);
     } else {
         *c = 0;
         s->r[R_SR] |= UART_SR_INTR_REMPTY;
-- 
1.7.0.4


Reply via email to