Hi Andreas, just a question. Due to the fact that we don't have the FPU on our Cortex-R4 and that we don't plan using floating point do you mind that we may use it even with the VFPv3-D16 vs. VFPv3-S32 issue?
Thanks and Best Regads Giancarlo > -----Original Message----- > From: Andreas Färber [mailto:afaer...@suse.de] > Sent: venerdì 21 settembre 2012 19:05 > To: Giancarlo ASNAGHI > Cc: qemu-devel@nongnu.org; Peter Maydell; Cedric VINCENT > Subject: Re: [Qemu-devel] ARM Cortex-R4 support ? > > Hello Giancarlo, > > Am 21.09.2012 17:15, schrieb Giancarlo ASNAGHI: > > Do you know which is the status of the support for Cortex-R4 support? I've > seen an initial set of patches from Andreas Farber one years ago, but into the > qemu-system-arm the Cortex-R4 ins't available yet. > > That's true. As a consequence of my patches we redesigned several parts of > ARM CPU modelling to facilitate this. My patches were not yet rebased onto > that. A new QOM type derived from TYPE_ARM_CPU would need to be > created now, to initialize the registers imperatively rather than > declaratively. > I might manage that quickly. > > Note that my published patches only took care of CPUID, FPU and a few > others to instantiate the -cpu cortex-r4 at all. > > Where I got stuck was reading through the ARMv7 TRM differences between > VMSA and PMSA (chapters B3 and B4 respectively) to implement PMSA, > pointed out by Peter. And there were also some floating point width > differences to ARMv7-A (VFPv3-D16 vs. VFPv3-S32 or so). > Neither is a small patch that I can supply short-term, maybe your colleagues > can help with those parts once I've refreshed my patches? > Cédric has worked on the FPU before, cc'ing. > > Regards, > Andreas > > -- > SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany > GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
