On Sun, Sep 9, 2012 at 8:38 PM, Max Filippov <jcmvb...@gmail.com> wrote: > On Sun, Sep 9, 2012 at 8:16 PM, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> On 9 September 2012 17:04, Max Filippov <jcmvb...@gmail.com> wrote: >>> These are FP to integer and integer to FP conversion opcodes. >>> See ISA, 4.3.10 for more details. >>> >>> Note that utrunc.s implementation follows ISS behaviour, not ISA. >> >> ISS here means "instruction set simulator", right? Do you >> have any actual silicon you can check behaviour against? >> Basically there are three votes here (documentation, simulator >> and silicon) and QEMU should follow the majority opinion in >> the absence of any more official word.
Short summary for the answer that I've got from Tensilica is the following: - hardware and ISS behaviour must match, - documentation (ISA) is wrong and will be fixed. > I have no silicon core with FP and I doubt that I can easily access one. > IIUC Tensilica ISS core-specific code is autogenerated from the hardware > description, without human intervention. > Looks like it's either documentation error or silicon error, probably > there's an erratum issued. Marc, can you please comment? -- Thanks. -- Max
