Hi Daniel and Alistair,
On 4/8/26 5:33 PM, Daniel Henrique Barboza wrote:
Gentlemen,
This is fully reviewed and good to go. Maybe needs a rebase since it
was last posted back in November.
Zhiwei, if you could please send a rebase keeping all acks that would be
terrific.
Thanks for the review and suggestion.
I have rebased the series on top of the latest tree and sent out v5. All
previously received Acked-by/Reviewed-by tags have been kept.
https://patchew.org/QEMU/[email protected]/diff/[email protected]/
Thanks,
Zhiwei
Cheers,
Daniel
On 11/12/2025 3:49 AM, LIU Zhiwei wrote:
This patch set introduces support for the RISC-V Smmpt (Supervisor
Memory-tracking and Protection Table) extension. Smmpt provides a
hardware mechanism for fine-grained memory protection, checked after
address translation, which is particularly useful for supervisor-level
sandboxing and security monitoring.
The rfc patch set:
https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
v3->v4:
1. Add missing review tags.
v2->v3:
1. Fix build error in patch 2.
2. Rebase to master.
rfc->v2:
1. When ext_smmpt is false or BARE mode, make other fields in mmpt
CSR zero.
2. Add patch 5 to fix smrnmi ISA string order.
3. Fix patch 6 smmpt and smsdid ISA string order.
4. Make smmpt and smsdid experiment extensions.
5. Add review tags.
LIU Zhiwei (6):
target/riscv: Add basic definitions and CSRs for SMMPT
target/riscv: Implement core SMMPT lookup logic
target/riscv: Integrate SMMPT checks into MMU and TLB fill
target/riscv: Implement SMMPT fence instructions
target/riscv: Fix smrnmi isa alphabetical order
target/riscv: Enable SMMPT extension
target/riscv/cpu.c | 6 +-
target/riscv/cpu.h | 9 +-
target/riscv/cpu_bits.h | 27 ++
target/riscv/cpu_cfg_fields.h.inc | 2 +
target/riscv/cpu_helper.c | 81 +++++-
target/riscv/csr.c | 95 ++++++
target/riscv/insn32.decode | 2 +
.../riscv/insn_trans/trans_privileged.c.inc | 30 ++
target/riscv/meson.build | 1 +
target/riscv/pmp.h | 3 +
target/riscv/riscv_smmpt.c | 274 ++++++++++++++++++
target/riscv/riscv_smmpt.h | 36 +++
12 files changed, 560 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/riscv_smmpt.c
create mode 100644 target/riscv/riscv_smmpt.h
