On Sun, 27 Jul 2025 at 08:42, Richard Henderson <richard.hender...@linaro.org> wrote: > > From: Gustavo Romero <gustavo.rom...@linaro.org> > > Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a > first step to fully support FEAT_MEC. > > The FEAT_MEC is an extension to FEAT_RME that implements multiple > Memory Encryption Contexts (MEC) so the memory in a realm can be > encrypted and accessing it from the wrong encryption context is not > possible. An encryption context allow the selection of a memory > encryption engine. > > At this point, no real memory encryption is supported, but software > stacks that rely on FEAT_MEC should work properly. > > Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Message-ID: <20250711140828.1714666-7-gustavo.rom...@linaro.org> > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/tcg/cpu64.c | 1 + > docs/system/arm/emulation.rst | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c > index 4eb51420ef..c54aa528c6 100644 > --- a/target/arm/tcg/cpu64.c > +++ b/target/arm/tcg/cpu64.c > @@ -1250,6 +1250,7 @@ void aarch64_max_tcg_initfn(Object *obj) > t = GET_IDREG(isar, ID_AA64MMFR3); > t = FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ > t = FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ > + t = FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ > t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ > SET_IDREG(isar, ID_AA64MMFR3, t);
Looking at this again, I don't think we should set ID_AA64MMFR3_EL1.MEC if RME is not enabled. I guess the way to do this that fits in with how we already handle "user-facing property disabled feature X and that means we should also disable feature Y" is to put a check in arm_cpu_realizefn() for "if RME disabled then squash ID_AA64MMFR3.MEC to 0" ? thanks -- PMM
