On Sun, 27 Jul 2025 at 08:42, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> From: Gustavo Romero <gustavo.rom...@linaro.org>
>
> Add all FEAT_MEC registers. Enable access to the registers via the
> SCTLR2 and TCR2 control bits. Add the two new cache management
> instructions, which are nops in QEMU because we do not model caches.
>
> Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
> Message-ID: <20250711140828.1714666-3-gustavo.rom...@linaro.org>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> [rth: Squash 3 patches to add all registers at once.]
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Phil just mentioned something on IRC which reminded me that there's
a quirk in the FEAT_MEC registers that we need to account for in
our FEAT_NV handling. We wrote a note for ourselves for later about
this in arm_cpreg_traps_in_nv():
* In particular, note that the released sysreg XML defines that
* the FEAT_MEC sysregs and instructions do not follow this FEAT_NV
* trapping rule, so we will need to add an ARM_CP_* flag to indicate
* "register does not trap on NV" to handle those if/when we implement
* FEAT_MEC.
(the "rule" being "trap on opc1 == 4 or 5"). This corresponds to
the text in the description of the HCR_EL2.NV bit in the Arm ARM
that says it traps:
— Registers accessed using MRS or MSR with a name ending in _EL2,
except the following:
— SP_EL2.
— If FEAT_MEC is implemented, MECID_A0_EL2, MECID_A1_EL2,
MECID_P0_EL2, MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, and
VMECID_P_EL2.
The system insns DC CIDGPAE and DC CIPAE also should not trap
(though the Arm ARM text is more implicit in how it says this
than it is for the registers).
So we need to:
* define a new ARM_CP_NV2_NO_TRAP ("This sysreg does not got
trapped to EL2 by HCR_EL2.NV even though its opc1 is in {4, 5}")
* have arm_cpreg_traps_in_nv() return false if
ri->type has ARM_CP_NV2_NO_TRAP set (and update the comment)
* add that to the type for all the sysregs defined by this
patch that have opc1 == 4 or 5
thanks
-- PMM
