From: Kane-Chen-AS <kane_c...@aspeedtech.com> This patch series introduces a QEMU model for the ASPEED OTP (One-Time Programmable) memory, along with its integration into the Secure Boot Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or device configuration, implemented with internal buffers; external file/device support not included in this version. It exposes an AddressSpace to support transaction-based access from controllers like the SBC. This series includes: - OTP memory device implementation - SBC integration with command decoding (READ/PROG) - Direct integration in AST2600 SoC without requiring user parameters Any feedback or suggestions are appreciated! Kane --- ChangeLog --------- v3: - Switched to object_property_set_int() for setting "size" - Simplified qdev_realize() error handling by passing errp directly - Added "drive" property to OTP model for future extensibility v2: - Rename device from 'aspeed_otpmem' to 'aspeed_otp' and move it to hw/nvram/ - Move OTP device realization from instance_init to the realize function - Improve error logging with qemu_log_mask() and remove unused error propagation v1: - Initial version --- Kane-Chen-AS (3): hw/misc/aspeed_otp: Add OTP device model with fallback RAM storage hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs include/hw/misc/aspeed_sbc.h | 5 ++ include/hw/nvram/aspeed_otp.h | 33 ++++++++++ hw/arm/aspeed_ast2600.c | 2 +- hw/misc/aspeed_sbc.c | 113 ++++++++++++++++++++++++++++++++++ hw/nvram/aspeed_otp.c | 113 ++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 5 ++ hw/nvram/meson.build | 4 ++ 7 files changed, 274 insertions(+), 1 deletion(-) create mode 100644 include/hw/nvram/aspeed_otp.h create mode 100644 hw/nvram/aspeed_otp.c -- 2.43.0
