On 5/27/25 8:24 AM, Ben Dooks wrote:
Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
Signed-off-by: Ben Dooks <ben.do...@codethink.co.uk>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..3daf75568c 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -34,6 +34,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
+#define TYPE_RISCV_CPU_CVA6 RISCV_CPU_TYPE_NAME("cva6")
#define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i")
#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e")
#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 629ac37501..fca45dc9d9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3009,6 +3009,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_CVA6, TYPE_RISCV_VENDOR_CPU,
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVS | RVU,
+ .misa_mxl_max = MXL_RV64,
+ .cfg.max_satp_mode = VM_1_10_SV39,
+ .priv_spec = PRIV_VERSION_1_12_0,
+ .cfg.pmp = true,
+ .cfg.mmu = true,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ ),
+
The CPU is being added inside a "#if defined(TARGET_RISCV64)" block, meaning
that it's a 64-bit CPU only. But the CVA6 board added in patch 1 is being
added for both 32 and 64 bit emulations in hw/riscv/Kconfig:
config CVA6
bool
default y
depends on RISCV32 || RISCV64 <------------------
This setup (after patch 3 is added) triggered a test failure in 'check-qtest',
when polling all available boards in qemu-system-riscv32, because it didn't find
a default 32 bit CPU for the cva6 board:
# starting QEMU: exec ./qemu-system-riscv32 -qtest unix:/tmp/qtest-1683816.sock
-qtest-log /dev/null -chardev socket,path=/tmp/qtest-1683816.qmp,id=char0 -mon
chardev=char0,mode=control -display none -audio none -machine cva6 -accel qtest
----------------------------------- stderr -----------------------------------
qemu-system-riscv32: ../hw/core/machine.c:1574: is_cpu_type_supported:
Assertion `cc != NULL' failed.
Broken pipe
../tests/qtest/libqtest.c:208: kill_qemu() detected QEMU death from signal 6
(Aborted) (core dumped)
We have 2 options here:
- if the CVA6 board is supposed to run in RISCV32 and RISCV64, then its default
CPU must be 32 bit compliant too. The CPU declaration in this patch must be
moved
outside the "#if defined(TARGET_RISCV64)" block (e.g right after
TYPE_RISCV_CPU_SIFIVE_U);
- if the board is 64 bit only then the CPU declaration is fine, and we need to
change the board hw/riscv/Kconfig entry to "depends on RISCV64".
Thanks,
Daniel
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV64
),
