Hi Cédric > Subject: Re: [PATCH v3 00/28] Fix incorrect hash results on AST2700 > > Hello Michael > > On 5/29/25 09:29, Michael Tokarev wrote: > > On 15.05.2025 11:09, Jamin Lin via wrote: > > > >> This patchset resolves incorrect hash results reported on the AST2700 > platform. > >> This update addresses the following kernel warnings and test failures > >> related to the crypto self-test framework: > > .. > >> Jamin Lin (28): > >> hw/misc/aspeed_hace: Remove unused code for better readability > >> hw/misc/aspeed_hace: Improve readability and consistency in > >> variable > >> naming > >> hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent > >> firmware > >> hang > >> hw/misc/aspeed_hace: Extract direct mode hash buffer setup into > >> helper > >> function > >> hw/misc/aspeed_hace: Extract SG-mode hash buffer setup into helper > >> function > >> hw/misc/aspeed_hace: Extract digest write and iov unmap into > >> helper > >> function > >> hw/misc/aspeed_hace: Extract non-accumulation hash execution into > >> helper function > >> hw/misc/aspeed_hace: Extract accumulation-mode hash execution > into > >> helper function > >> hw/misc/aspeed_hace: Introduce 64-bit hash source address helper > >> function > >> hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST > and > >> introduce > >> 64-bit hash digest address helper > >> hw/misc/aspeed_hace: Support accumulative mode for direct access > >> mode > >> hw/misc/aspeed_hace: Move register size to instance class and > >> dynamically allocate regs > >> hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 > >> bit > >> addresses > >> hw/misc/aspeed_hace: Support DMA 64 bits dram address > >> hw/misc/aspeed_hace: Add trace-events for better debugging > >> hw/misc/aspeed_hace: Support to dump plaintext and digest for > >> better > >> debugging > >> tests/qtest: Reorder aspeed test list > >> test/qtest: Introduce a new aspeed-hace-utils.c to place common > >> testcases > >> test/qtest/hace: Specify explicit array sizes for test vectors and > >> hash results > >> test/qtest/hace: Adjust test address range for AST1030 due to SRAM > >> limitations > >> test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model > >> test/qtest/hace: Add SHA-384 tests for AST2600 > >> test/qtest/hace: Add tests for AST1030 > >> test/qtest/hace: Update source data and digest data type to 64-bit > >> test/qtest/hace: Support 64-bit source and digest addresses for > >> AST2700 > >> test/qtest/hace: Support to test upper 32 bits of digest and > >> source > >> addresses > >> test/qtest/hace: Support to validate 64-bit hmac key buffer > >> addresses > >> test/qtest/hace: Add tests for AST2700 > > > > Is there anything here which is worth to apply to qemu-stable (10.0.x > > is supposed to be LTS series)? > > > The candidates would be these two : > > hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to > hw/arm/aspeed_ast27x0: Fix RAM size detection failure on > > Jamin, > > Do you agree ? >
Agree Thanks-Jamin > Thanks, > > C. >
