[Stable-9.2.4 44/62] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

[Michael Tokarev]

From: Max Chou <max.c...@sifive.com>

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <ant...@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Signed-off-by: Max Chou <max.c...@sifive.com>
Message-ID: <20250408103938.3623486-6-max.c...@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Cc: qemu-sta...@nongnu.org
(cherry picked from commit fda68acb7761af40df78db18e44ca1ff20195fe0)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index e8197f779e..2a4bededd1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -432,6 +432,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, 
int vm)
 static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
     return vext_check_ss(s, vd, vs2, vm) &&
+           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
            require_align(vs1, s->lmul);
 }
 
-- 
2.39.5