On 4/17/2025 3:22 AM, Dongli Zhang wrote: > Since perfmon-v2, the AMD PMU supports additional registers. This update > includes get/put functionality for these extra registers. > > Similar to the implementation in KVM: > > - MSR_CORE_PERF_GLOBAL_STATUS and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS both > use env->msr_global_status. > - MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use > env->msr_global_ctrl. > - MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR > both use env->msr_global_ovf_ctrl. > > No changes are needed for vmstate_msr_architectural_pmu or > pmu_enable_needed(). > > Signed-off-by: Dongli Zhang <dongli.zh...@oracle.com> > Reviewed-by: Zhao Liu <zhao1....@intel.com> > --- > Changed since v1: > - Use "has_pmu_version > 1", not "has_pmu_version == 2". > Changed since v2: > - Use cpuid_find_entry() instead of cpu_x86_cpuid(). > - Change has_pmu_version to pmu_version. > - Cap num_pmu_gp_counters with MAX_GP_COUNTERS. > > target/i386/cpu.h | 4 ++++ > target/i386/kvm/kvm.c | 48 +++++++++++++++++++++++++++++++++++-------- > 2 files changed, 43 insertions(+), 9 deletions(-) >
Reviewed-by: Sandipan Das <sandipan....@amd.com>
