On Wed, Apr 16, 2025 at 02:52:34PM -0700, Dongli Zhang wrote: > Date: Wed, 16 Apr 2025 14:52:34 -0700 > From: Dongli Zhang <dongli.zh...@oracle.com> > Subject: [PATCH v4 09/11] target/i386/kvm: reset AMD PMU registers during > VM reset > X-Mailer: git-send-email 2.43.5 > > QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM > and kvm_put_msrs() to restore them to KVM. However, there is no support for > AMD PMU registers. Currently, pmu_version and num_pmu_gp_counters are > initialized based on cpuid(0xa), which does not apply to AMD processors. > For AMD CPUs, prior to PerfMonV2, the number of general-purpose registers > is determined based on the CPU version. > > To address this issue, we need to add support for AMD PMU registers. > Without this support, the following problems can arise: > > 1. If the VM is reset (e.g., via QEMU system_reset or VM kdump/kexec) while > running "perf top", the PMU registers are not disabled properly. > > 2. Despite x86_cpu_reset() resetting many registers to zero, kvm_put_msrs() > does not handle AMD PMU registers, causing some PMU events to remain > enabled in KVM. > > 3. The KVM kvm_pmc_speculative_in_use() function consistently returns true, > preventing the reclamation of these events. Consequently, the > kvm_pmc->perf_event remains active. > > 4. After a reboot, the VM kernel may report the following error: > > [ 0.092011] Performance Events: Fam17h+ core perfctr, Broken BIOS > detected, complain to your hardware vendor. > [ 0.092023] [Firmware Bug]: the BIOS has corrupted hw-PMU resources (MSR > c0010200 is 530076) > > 5. In the worst case, the active kvm_pmc->perf_event may inject unknown > NMIs randomly into the VM kernel: > > [...] Uhhuh. NMI received for unknown reason 30 on CPU 0. > > To resolve these issues, we propose resetting AMD PMU registers during the > VM reset process. > > Signed-off-by: Dongli Zhang <dongli.zh...@oracle.com> > --- > Changed since v1: > - Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using > AMD64_NUM_COUNTERS (suggested by Sandipan Das). > - Use "AMD64_NUM_COUNTERS_CORE * 2 - 1", not "MSR_F15H_PERF_CTL0 + 0xb". > (suggested by Sandipan Das). > - Switch back to "-pmu" instead of using a global "pmu-cap-disabled". > - Don't initialize PMU info if kvm.enable_pmu=N. > Changed since v2: > - Remove 'static' from host_cpuid_vendorX. > - Change has_pmu_version to pmu_version. > - Use object_property_get_int() to get CPU family. > - Use cpuid_find_entry() instead of cpu_x86_cpuid(). > - Send error log when host and guest are from different vendors. > - Move "if (!cpu->enable_pmu)" to begin of function. Add comments to > reminder developers. > - Add support to Zhaoxin. Change is_same_vendor() to > is_host_compat_vendor(). > - Didn't add Reviewed-by from Sandipan because the change isn't minor. > Changed since v3: > - Use host_cpu_vendor_fms() from Zhao's patch. > - Check AMD directly makes the "compat" rule clear. > - Add comment to MAX_GP_COUNTERS. > - Skip PMU info initialization if !kvm_pmu_disabled. > > target/i386/cpu.h | 12 +++ > target/i386/kvm/kvm.c | 175 +++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 183 insertions(+), 4 deletions(-)
Reviewed-by: Zhao Liu <zhao1....@intel.com>
