On Sun, Apr 6, 2025 at 5:04 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------
> 1 file changed, 35 insertions(+), 40 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 616d89be17e..4e4d8ddf5a2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -500,45 +500,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu,
> const RISCVCSR *csr_list)
> #endif
>
> #if defined(TARGET_RISCV64)
> -static void rv64_veyron_v1_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);
> - env->priv_ver = PRIV_VERSION_1_12_0;
> -
> - /* Enable ISA extensions */
> - cpu->cfg.mmu = true;
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.pmp = true;
> - cpu->cfg.ext_zicbom = true;
> - cpu->cfg.cbom_blocksize = 64;
> - cpu->cfg.cboz_blocksize = 64;
> - cpu->cfg.ext_zicboz = true;
> - cpu->cfg.ext_smaia = true;
> - cpu->cfg.ext_ssaia = true;
> - cpu->cfg.ext_sscofpmf = true;
> - cpu->cfg.ext_sstc = true;
> - cpu->cfg.ext_svinval = true;
> - cpu->cfg.ext_svnapot = true;
> - cpu->cfg.ext_svpbmt = true;
> - cpu->cfg.ext_smstateen = true;
> - cpu->cfg.ext_zba = true;
> - cpu->cfg.ext_zbb = true;
> - cpu->cfg.ext_zbc = true;
> - cpu->cfg.ext_zbs = true;
> - cpu->cfg.ext_XVentanaCondOps = true;
> -
> - cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
> - cpu->cfg.marchid = VEYRON_V1_MARCHID;
> - cpu->cfg.mimpid = VEYRON_V1_MIMPID;
> -
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_SV48);
> -#endif
> -}
>
> static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> {
> @@ -3211,7 +3172,41 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.max_satp_mode = VM_1_10_SV57,
> ),
>
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
> rv64_veyron_v1_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU,
> + .misa_mxl_max = MXL_RV64,
> + .misa_ext = RVG | RVC | RVS | RVU | RVH,
> + .priv_spec = PRIV_VERSION_1_12_0,
> +
> + /* ISA extensions */
> + .cfg.mmu = true,
> + .cfg.ext_zifencei = true,
> + .cfg.ext_zicsr = true,
> + .cfg.pmp = true,
> + .cfg.ext_zicbom = true,
> + .cfg.cbom_blocksize = 64,
> + .cfg.cboz_blocksize = 64,
> + .cfg.ext_zicboz = true,
> + .cfg.ext_smaia = true,
> + .cfg.ext_ssaia = true,
> + .cfg.ext_sscofpmf = true,
> + .cfg.ext_sstc = true,
> + .cfg.ext_svinval = true,
> + .cfg.ext_svnapot = true,
> + .cfg.ext_svpbmt = true,
> + .cfg.ext_smstateen = true,
> + .cfg.ext_zba = true,
> + .cfg.ext_zbb = true,
> + .cfg.ext_zbc = true,
> + .cfg.ext_zbs = true,
> + .cfg.ext_XVentanaCondOps = true,
> +
> + .cfg.mvendorid = VEYRON_V1_MVENDORID,
> + .cfg.marchid = VEYRON_V1_MARCHID,
> + .cfg.mimpid = VEYRON_V1_MIMPID,
> +
> + .cfg.max_satp_mode = VM_1_10_SV48,
> + ),
> +
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
> MXL_RV64,
> rv64_xiangshan_nanhu_cpu_init),
> #ifdef CONFIG_TCG
> --
> 2.49.0
>
