On Sun, Apr 6, 2025 at 5:04 PM Paolo Bonzini <pbonz...@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 80 +++++++++++++---------------------------------
> 1 file changed, 23 insertions(+), 57 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4e4d8ddf5a2..0a3a0343087 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -441,16 +441,6 @@ const char *satp_mode_str(uint8_t satp_mode, bool
> is_32_bit)
> g_assert_not_reached();
> }
>
> -static void __attribute__((unused))
> -set_satp_mode_max_supported(RISCVCPU *cpu, int satp_mode)
> -{
> - bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
> - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
> -
> - assert(valid_vm[satp_mode]);
> - cpu->cfg.max_satp_mode = satp_mode;
> -}
> -
> static bool get_satp_mode_supported(RISCVCPU *cpu, uint16_t *supported)
> {
> bool rv32 = riscv_cpu_is_32bit(cpu);
> @@ -499,38 +489,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu,
> const RISCVCSR *csr_list)
> }
> #endif
>
> -#if defined(TARGET_RISCV64)
> -
> -static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
> - env->priv_ver = PRIV_VERSION_1_12_0;
> -
> - /* Enable ISA extensions */
> - cpu->cfg.ext_zbc = true;
> - cpu->cfg.ext_zbkb = true;
> - cpu->cfg.ext_zbkc = true;
> - cpu->cfg.ext_zbkx = true;
> - cpu->cfg.ext_zknd = true;
> - cpu->cfg.ext_zkne = true;
> - cpu->cfg.ext_zknh = true;
> - cpu->cfg.ext_zksed = true;
> - cpu->cfg.ext_zksh = true;
> - cpu->cfg.ext_svinval = true;
> -
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_SV39);
> -#endif
> -}
> -
> -#endif /* !TARGET_RISCV64 */
> -
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> {
> ObjectClass *oc;
> @@ -2895,19 +2853,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt,
> char *nodename)
> }
> #endif
>
> -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
> - { \
> - .name = (type_name), \
> - .parent = TYPE_RISCV_VENDOR_CPU, \
> - .instance_init = (initfn), \
> - .class_data = (void*) &((const RISCVCPUDef) { \
> - .misa_mxl_max = (misa_mxl_max_), \
> - .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
> - .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
> - .cfg.max_satp_mode = -1, \
> - }), \
> - }
> -
> #define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
> { \
> .name = (type_name), \
> @@ -3207,8 +3152,29 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.max_satp_mode = VM_1_10_SV48,
> ),
>
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
> - MXL_RV64,
> rv64_xiangshan_nanhu_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU,
> + .misa_mxl_max = MXL_RV64,
> + .misa_ext = RVG | RVC | RVB | RVS | RVU,
> + .priv_spec = PRIV_VERSION_1_12_0,
> +
> + /* ISA extensions */
> + .cfg.ext_zbc = true,
> + .cfg.ext_zbkb = true,
> + .cfg.ext_zbkc = true,
> + .cfg.ext_zbkx = true,
> + .cfg.ext_zknd = true,
> + .cfg.ext_zkne = true,
> + .cfg.ext_zknh = true,
> + .cfg.ext_zksed = true,
> + .cfg.ext_zksh = true,
> + .cfg.ext_svinval = true,
> +
> + .cfg.mmu = true,
> + .cfg.pmp = true,
> +
> + .cfg.max_satp_mode = VM_1_10_SV39,
> + ),
> +
> #ifdef CONFIG_TCG
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
> .cfg.max_satp_mode = VM_1_10_SV57,
> --
> 2.49.0
>
