On 4/3/25 19:52, Brian Cain wrote:
From: Brian Cain <bc...@quicinc.com>
Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
---
target/hexagon/cpu-param.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b4640..ccaf6a9d28 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -23,4 +23,9 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+/*
+ * Hexagon processors have a strong memory model.
+ */
+#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL)
+
#endif
Excellent, then we have that covered with
https://patchew.org/QEMU/20250321181549.3331-1-phi...@linaro.org/20250321181549.3331-2-phi...@linaro.org/
and the follow-up
https://patchew.org/QEMU/20250321181549.3331-1-phi...@linaro.org/20250321181549.3331-8-phi...@linaro.org/
which moves that macro to a field in TCGCPUOps.
r~
