On 3/19/25 5:48 AM, Shameerali Kolothum Thodi wrote:
-----Original Message-----
From: Donald Dutile <ddut...@redhat.com>
Sent: Wednesday, March 19, 2025 1:31 AM
To: Shameerali Kolothum Thodi
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Subject: Re: [RFC PATCH v2 13/20] hw/arm/smmuv3-accel: Introduce helpers
to batch and issue cache invalidations
Shameer,
Hi,
On 3/11/25 10:10 AM, Shameer Kolothum wrote:
From: Nicolin Chen <nicol...@nvidia.com>
Inroduce an SMMUCommandBatch and some helpers to batch and issue
the
^^^^^^^^ Introduce
commands. Currently separate out TLBI commands and device cache
commands to avoid some errata on certain versions of SMMUs. Later it
should check IIDR register to detect if underlying SMMU hw has such an
erratum.
Where is all this info about 'certain versions of SMMUs' and 'check IIDR
register' has something to do with 'underlying SMMU hw such an erratum',
-- which IIDR (& bits)? or are we talking about rsvd SMMU_IDR<> registers?
I guess the batching has constraints on some platforms, IIRC, this was discussed
somewhere in a kernel thread.
Nicolin, could you please provide some background on this.
A lore link if it's discussed upstream, thanks.
And can't these helpers be used for emulated smmuv3 as well as
accelerated?
Could be I guess. But no benefit in terms of performance. May be will make
code look nicer. I will take a look if not much of changes in the emulated path.
Thanks for looking into it. The push is to use common code path(s) to invoke
(or not)
an accel path.
Thanks,
Shameer
