On Wed, Mar 19, 2025 at 12:24:32PM -0400, Donald Dutile wrote: > > > On 3/11/25 10:10 AM, Shameer Kolothum wrote: > > > > From: Nicolin Chen <nicol...@nvidia.com> > > > > > > > > Inroduce an SMMUCommandBatch and some helpers to batch and issue > > > the > > > ^^^^^^^^ Introduce > > > > commands. Currently separate out TLBI commands and device cache > > > > commands to avoid some errata on certain versions of SMMUs. Later it > > > > should check IIDR register to detect if underlying SMMU hw has such an > > > erratum. > > > Where is all this info about 'certain versions of SMMUs' and 'check IIDR > > > register' has something to do with 'underlying SMMU hw such an erratum', > > > -- which IIDR (& bits)? or are we talking about rsvd SMMU_IDR<> registers? > > > > I guess the batching has constraints on some platforms, IIRC, this was > > discussed > > somewhere in a kernel thread. > > > > Nicolin, could you please provide some background on this. > > > A lore link if it's discussed upstream, thanks.
https://lore.kernel.org/all/696da78d32bb4491f898f11b0bb4d850a8aa7c6a.1683731256.git.robin.mur...@arm.com/ IIRC, some of them forbid command issuing like mixing leaf TLBI commands with non-leaf TLBI commands or mixing device commands with TLBI commands. Currently, kernel masks away the ARM_SMMU_FEAT_NESTING from the affected SMMU versions/subversions. So, I think we are fine for now, though probably doesn't hurt to check IIDR? Thanks Nicolin
