On Thu, Feb 13, 2025 at 03:09:05PM +0800, Yuquan Wang wrote:
> On Tue, Feb 11, 2025 at 09:26:55AM +0000, Jonathan Cameron wrote:
> > On Tue, 11 Feb 2025 10:24:13 +0800
> > Yuquan Wang <wangyuquan1...@phytium.com.cn> wrote:
> >
> > > The previous default value of sn is UI64_NULL which would cause the
> > > cookie of nd_interleave_set be '0' and the "invalid interleave-set
> > > -cookie" failure in label validation.
> > Hi Yuquan,
> >
> > Maybe we should harden the nd_interleave_set code to fail
> > to set the cookie in the event of no serial number. That is a
> > device not compliant with the spec, but none the less it is not
> > implausible with test devices etc.
> >
> Thanks for your suggestions :)
>
> I have send patch 'cxl/pmem: debug invalid serial number data' trying to
> fix this problem. Welcome more comments to guide me!
>
> link:
> https://lore.kernel.org/linux-cxl/20250213064008.4032730-1-wangyuquan1...@phytium.com.cn/T/#t
>
> Here I have another question about labels. It seems like current kernel
> only deals with nvdimm namespaces labels and leaves cxl region labels to
> do. Therefore, for some dynamically-created cxl pmem regions, users have
> to re-create these regions manually. Does it means CXL drivers could not
> recover
> a cxl region by cxl region lables now?.
As you mentioned, region label is not implemented in current kernel, so
I do not see a way to recover a region with region label as it is not
persisted to the LSA of the device.
Fan
> > >
> > > As many users maybe not know how to set a unique sn for cxl-type3
> > > device and perhaps be confuesd by the failure of label validation,
> > > so this defines '1' as the default value of serial number to fix the
> > > problem.
> >
> > That magic value is specifically chosen to be 'undefined' to trigger
> > clean handling of the failure and not provide the serial number
> > capability.
> >
> > If you have multiple devices and provide a 'valid' default then
> > there are circumstances in which the device will be seen as a multiheaded
> > single device attached to two places in the PCI topology.
> >
> > So I'm not keen to change this. Ideally we'd have made this a required
> > parameter from the start, but we didn't and doing so now would result
> > in a backwards compatibility problem.
> >
> > So I think this is kind of a 'won't fix' situation on the qemu side.
> Ok, I see.
>
> Maybe we could modify the Example command lines in docs/../cxl.rst to remind
> users to add this parameter. Is this feasible?
>
> >
> > Jonathan
> >
> > >
> > > Signed-off-by: Yuquan Wang <wangyuquan1...@phytium.com.cn>
> > > ---
> > > hw/mem/cxl_type3.c | 17 ++++-------------
> > > 1 file changed, 4 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> > > index 0ae1704a34..a6b5a9f74e 100644
> > > --- a/hw/mem/cxl_type3.c
> > > +++ b/hw/mem/cxl_type3.c
> > > @@ -310,12 +310,6 @@ static void ct3d_config_write(PCIDevice *pci_dev,
> > > uint32_t addr, uint32_t val,
> > > pcie_aer_write_config(pci_dev, addr, val, size);
> > > }
> > >
> > > -/*
> > > - * Null value of all Fs suggested by IEEE RA guidelines for use of
> > > - * EU, OUI and CID
> > > - */
> > > -#define UI64_NULL ~(0ULL)
> > > -
> > > static void build_dvsecs(CXLType3Dev *ct3d)
> > > {
> > > CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
> > > @@ -856,12 +850,9 @@ static void ct3_realize(PCIDevice *pci_dev, Error
> > > **errp)
> > > pci_config_set_prog_interface(pci_conf, 0x10);
> > >
> > > pcie_endpoint_cap_init(pci_dev, 0x80);
> > > - if (ct3d->sn != UI64_NULL) {
> > > - pcie_dev_ser_num_init(pci_dev, 0x100, ct3d->sn);
> > > - cxl_cstate->dvsec_offset = 0x100 + 0x0c;
> > > - } else {
> > > - cxl_cstate->dvsec_offset = 0x100;
> > > - }
> > > +
> > > + pcie_dev_ser_num_init(pci_dev, 0x100, ct3d->sn);
> > > + cxl_cstate->dvsec_offset = 0x100 + 0x0c;
> > >
> > > ct3d->cxl_cstate.pdev = pci_dev;
> > > build_dvsecs(ct3d);
> > > @@ -1225,7 +1216,7 @@ static const Property ct3_props[] = {
> > > TYPE_MEMORY_BACKEND, HostMemoryBackend *),
> > > DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
> > > HostMemoryBackend *),
> > > - DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL),
> > > + DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, 0x1),
> > > DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename),
> > > DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0),
> > > DEFINE_PROP_LINK("volatile-dc-memdev", CXLType3Dev, dc.host_dc,
> >
>
