Accept AND, ext32u, ext32s extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
tcg/mips/tcg-target-has.h | 26 ++++++++++++++++++++++----
tcg/mips/tcg-target.c.inc | 33 ++++++++++++++++++++++++++++++---
2 files changed, 52 insertions(+), 7 deletions(-)
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
index d3d874ffd1..e7914cc970 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -80,8 +80,8 @@ extern bool use_mips32r2_instructions;
/* optional instructions detected at runtime */
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
-#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
-#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
+#define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
@@ -96,8 +96,8 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
-#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
-#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
+#define TCG_TARGET_HAS_sextract_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
@@ -119,4 +119,22 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 0
+#define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions
+
+static inline bool
+tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
+{
+ if (ofs == 0) {
+ switch (len) {
+ case 8:
+ case 16:
+ return use_mips32r2_instructions;
+ case 32:
+ return type == TCG_TYPE_I64;
+ }
+ }
+ return false;
+}
+#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
+
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index b31b8f0007..99f6ef6c76 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2041,12 +2041,37 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
args[3] + args[4] - 1, args[3]);
break;
+
case INDEX_op_extract_i32:
- tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
+ if (a2 == 0 && args[3] <= 16) {
+ tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
+ } else {
+ tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
+ }
break;
case INDEX_op_extract_i64:
- tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
- args[3] - 1, a2);
+ if (a2 == 0 && args[3] <= 16) {
+ tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
+ } else {
+ tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU,
+ a0, a1, args[3] - 1, a2);
+ }
+ break;
+
+ case INDEX_op_sextract_i64:
+ if (a2 == 0 && args[3] == 32) {
+ tcg_out_ext32s(s, a0, a1);
+ break;
+ }
+ /* FALLTHRU */
+ case INDEX_op_sextract_i32:
+ if (a2 == 0 && args[3] == 8) {
+ tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1);
+ } else if (a2 == 0 && args[3] == 16) {
+ tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1);
+ } else {
+ g_assert_not_reached();
+ }
break;
case INDEX_op_brcond_i32:
@@ -2170,6 +2195,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned
flags)
case INDEX_op_ext8s_i32:
case INDEX_op_ext16s_i32:
case INDEX_op_extract_i32:
+ case INDEX_op_sextract_i32:
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i64:
@@ -2191,6 +2217,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned
flags)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
--
2.43.0
