On Thu, Dec 12, 2024 at 06:22:02PM +0100, Paolo Bonzini wrote: > Date: Thu, 12 Dec 2024 18:22:02 +0100 > From: Paolo Bonzini <pbonz...@redhat.com> > Subject: [PATCH 5/7] rust: pl011: extend registers to 32 bits > X-Mailer: git-send-email 2.47.1 > > The PL011 Technical Reference Manual lists the "real" size of the > registers in table 3-1, and only rounds up to the next byte when > describing the registers; for example, UARTDR is listed as having > width 12/8 (12 bits read, 8 written) and only bits 15:0 are listed > in "Table 3-2 UARTDR Register". > > However, in practice these are 32-bit registers, accessible only > through 32-bit MMIO accesses; preserving the fiction that they're > smaller introduces multiple casts (to go from the bilge bitfield > type to e.g u16 to u64) and more importantly it breaks the > migration stream (though only on big-endian machines) because > the Rust vmstate macros are not yet type safe. > > So, just make everything 32-bits wide. > > Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> > --- > rust/hw/char/pl011/src/device.rs | 36 ++++++++++++++------------------ > rust/hw/char/pl011/src/lib.rs | 23 +++++++++----------- > 2 files changed, 26 insertions(+), 33 deletions(-) >
Reviewed-by: Zhao Liu <zhao1....@intel.com>
