Peter Maydell <peter.mayd...@linaro.org> writes: > On Fri, 6 Dec 2024 at 16:02, Alex Bennée <alex.ben...@linaro.org> wrote: >> >> When FEAT_SEL2 was implemented the SEL2 timers where missed. This >> shows up when building the latest Hafnium with SPMC_AT_EL=2. The >> actual implementation utilises the same logic as the rest of the >> timers so all we need to do is: >> >> - define the timers and their access functions >> - conditionally add the correct system registers >> - create a new accessfn as the rules are subtly different to the >> existing secure timer >> >> Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers) >> Signed-off-by: Alex Bennée <alex.ben...@linaro.org> >> Cc: qemu-sta...@nongnu.org >> Cc: Andrei Homescu <ahome...@google.com> >> Cc: Arve Hjønnevåg <a...@google.com> >> Cc: Rémi Denis-Courmont <remi.denis.courm...@huawei.com> >> >> --- >> v1 >> - add better comments to GTIMER descriptions >> - also define new timers for sbsa-ref >> - don't conditionally gate qemu_timer creation on the feature >> - take cntvoff_el2 int account for SEC_VEL2 in >> gt_recalc/g_tval_[read|write] >> --- >> include/hw/arm/bsa.h | 2 + >> target/arm/cpu.h | 2 + >> target/arm/gtimer.h | 4 +- >> hw/arm/sbsa-ref.c | 2 + >> hw/arm/virt.c | 2 + > > I would put the board changes in their own patch(es).
Won't that break bisection? -- Alex Bennée Virtualisation Tech Lead @ Linaro
