> -----Original Message----- > From: Peter Maydell <peter.mayd...@linaro.org> > Sent: Friday, December 13, 2024 1:33 PM > To: Jason Gunthorpe <j...@nvidia.com> > Cc: Daniel P. Berrangé <berra...@redhat.com>; Shameerali Kolothum > Thodi <shameerali.kolothum.th...@huawei.com>; qemu-...@nongnu.org; > qemu-devel@nongnu.org; eric.au...@redhat.com; nicol...@nvidia.com; > ddut...@redhat.com; Linuxarm <linux...@huawei.com>; Wangzhou (B) > <wangzh...@hisilicon.com>; jiangkunkun <jiangkun...@huawei.com>; > Jonathan Cameron <jonathan.came...@huawei.com>; > zhangfei....@linaro.org > Subject: Re: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable > nested SMMUv3 > > On Fri, 13 Dec 2024 at 12:46, Jason Gunthorpe <j...@nvidia.com> wrote: > > > > On Fri, Dec 13, 2024 at 12:00:43PM +0000, Daniel P. Berrangé wrote: > > > On Fri, Nov 08, 2024 at 12:52:37PM +0000, Shameer Kolothum via wrote: > > > > Hi, > > > > > > > > This series adds initial support for a user-creatable "arm-smmuv3- > nested" > > > > device to Qemu. At present the Qemu ARM SMMUv3 emulation is per > machine > > > > and cannot support multiple SMMUv3s. > > > > > > > > In order to support vfio-pci dev assignment with vSMMUv3, the > physical > > > > SMMUv3 has to be configured in nested mode. Having a pluggable > > > > "arm-smmuv3-nested" device enables us to have multiple vSMMUv3 > for Guests > > > > running on a host with multiple physical SMMUv3s. A few benefits of > doing > > > > this are, > > > > > > I'm not very familiar with arm, but from this description I'm not > > > really seeing how "nesting" is involved here. You're only talking > > > about the host and 1 L1 guest, no L2 guest. > > > > nesting is the term the iommu side is using to refer to the 2 > > dimensional paging, ie a guest page table on top of a hypervisor page > > table. > > Isn't that more usually called "two stage" paging? Calling > that "nesting" seems like it is going to be massively confusing...
Yes. This will be renamed in future revisions as arm-smmuv3-accel. > > Also, how does it relate to what this series seems to be > doing, where we provide the guest with two separate SMMUs? > (Are those two SMMUs "nested" in the sense that one is sitting > behind the other?) I don't think it requires two SMMUs in Guest. The nested or "two stage" means the stage 1 page table is owned by Guest and stage 2 by host. And this is achieved by IOMMUFD provided IOCTLs. There is a precurser to this series where the support for hw accelerated 2 stage support is added in Qemu SMMUv3 code. Please see the complete branch here, https://github.com/hisilicon/qemu/commits/private-smmuv3-nested-dev-rfc-v1/ And patches prior to this commit adds that support: 4ccdbe3: ("cover-letter: Add HW accelerated nesting support for arm SMMUv3") Nicolin is soon going to send out those for review. Or I can include those in this series so that it gives a complete picture. Nicolin? Hope this clarifies any confusion. Thanks, Shameer
