Hi, I fell into some strangeness while using RISCV: * firstly the rvi stores / loads don't seem to generate a trap when doing a misaligned access, which is something we would like to happen. According to the documentation an EEI may or may no guarantee misaligned loads and stores are handled invisibly. Thus PATCH 1 adds an option for enabling those traps, and PATCH 2 raise it when enabled and Zama16B (which implies atomicity for misaligned access within 16bytes boundary) is disabled.
* secondly about the conditional store: the documentation states that the Zalrsc extension requires that the address held in rs1 is naturally aligned to the size of the operand. The current implementation doesn't do that check if the store doesn't happen, so the third PATCH fixes that behavior so that a misaligned trap will happen if the address is not naturally aligned even if the store shouldn't happen. Best Regards, Fred Frederic Konrad (3): target/riscv: add a trap-misaligned-access property target/riscv: generate misaligned access trap for rvi insn target/riscv: fix the trap generation for conditional store target/riscv/cpu.c | 5 +++++ target/riscv/cpu_cfg.h | 1 + target/riscv/insn_trans/trans_rva.c.inc | 19 +++++++++++++++++++ target/riscv/insn_trans/trans_rvi.c.inc | 7 +++++++ 4 files changed, 32 insertions(+) -- 2.43.5
