Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate-a64.c | 34 ++++++----------------------------
target/arm/tcg/a64.decode | 4 ++++
2 files changed, 10 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 3e0c061b3c..aff1984a22 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8915,6 +8915,9 @@ static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a,
GVecGen2Fn *fn)
TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs)
TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
+TRANS(NOT_v, do_gvec_fn2, a, tcg_gen_gvec_not)
+TRANS(CNT_v, do_gvec_fn2, a, gen_gvec_cnt)
+TRANS(RBIT_v, do_gvec_fn2, a, gen_gvec_rbit)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
@@ -9229,12 +9232,6 @@ static void handle_2misc_64(DisasContext *s, int opcode,
bool u,
TCGCond cond;
switch (opcode) {
- case 0x5: /* NOT */
- /* This opcode is shared with CNT and RBIT but we have earlier
- * enforced that size == 3 if and only if this is the NOT insn.
- */
- tcg_gen_not_i64(tcg_rd, tcg_rn);
- break;
case 0xa: /* CMLT */
cond = TCG_COND_LT;
do_cmop:
@@ -9291,6 +9288,7 @@ static void handle_2misc_64(DisasContext *s, int opcode,
bool u,
break;
default:
case 0x4: /* CLS, CLZ */
+ case 0x5: /* NOT */
case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */
g_assert_not_reached();
@@ -10072,19 +10070,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
case 0x1: /* REV16 */
handle_rev(s, opcode, u, is_q, size, rn, rd);
return;
- case 0x5: /* CNT, NOT, RBIT */
- if (u && size == 0) {
- /* NOT */
- break;
- } else if (u && size == 1) {
- /* RBIT */
- break;
- } else if (!u && size == 0) {
- /* CNT */
- break;
- }
- unallocated_encoding(s);
- return;
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
if (size == 3) {
@@ -10302,6 +10287,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
default:
case 0x3: /* SUQADD, USQADD */
case 0x4: /* CLS, CLZ */
+ case 0x5: /* CNT, NOT, RBIT */
case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */
unallocated_encoding(s);
@@ -10324,15 +10310,6 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
switch (opcode) {
- case 0x5: /* CNT, NOT, RBIT */
- if (!u) {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cnt, 0);
- } else if (size) {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_rbit, 0);
- } else {
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
- }
- return;
case 0x8: /* CMGT, CMGE */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
@@ -10351,6 +10328,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
case 0x4: /* CLZ, CLS */
+ case 0x5: /* CNT, NOT, RBIT */
case 0xb:
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 32355ee633..bac81eec7e 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -71,6 +71,7 @@
@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3
@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3
+@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@@ -1643,3 +1644,6 @@ ABS_v 0.00 1110 ..1 00000 10111 0 ..... .....
@qrr_e
NEG_v 0.10 1110 ..1 00000 10111 0 ..... ..... @qrr_e
CLS_v 0.00 1110 ..1 00000 01001 0 ..... ..... @qrr_e
CLZ_v 0.10 1110 ..1 00000 01001 0 ..... ..... @qrr_e
+CNT_v 0.00 1110 001 00000 01011 0 ..... ..... @qrr_b
+NOT_v 0.10 1110 001 00000 01011 0 ..... ..... @qrr_b
+RBIT_v 0.10 1110 011 00000 01011 0 ..... ..... @qrr_b
--
2.43.0
