This includes CSEL, CSINC, CSINV, CSNEG. Remove disas_data_proc_reg,
as these were the last insns decoded by that function.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate-a64.c | 84 ++++++----------------------------
target/arm/tcg/a64.decode | 3 ++
2 files changed, 17 insertions(+), 70 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 56a445a3c2..9c6365f5ef 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8171,39 +8171,17 @@ static bool trans_CCMP(DisasContext *s, arg_CCMP *a)
return true;
}
-/* Conditional select
- * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
- * +----+----+---+-----------------+------+------+-----+------+------+
- * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
- * +----+----+---+-----------------+------+------+-----+------+------+
- */
-static void disas_cond_select(DisasContext *s, uint32_t insn)
+static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
{
- unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
- TCGv_i64 tcg_rd, zero;
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 zero = tcg_constant_i64(0);
DisasCompare64 c;
- if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
- /* S == 1 or op2<1> == 1 */
- unallocated_encoding(s);
- return;
- }
- sf = extract32(insn, 31, 1);
- else_inv = extract32(insn, 30, 1);
- rm = extract32(insn, 16, 5);
- cond = extract32(insn, 12, 4);
- else_inc = extract32(insn, 10, 1);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
+ a64_test_cc(&c, a->cond);
- tcg_rd = cpu_reg(s, rd);
-
- a64_test_cc(&c, cond);
- zero = tcg_constant_i64(0);
-
- if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
+ if (a->rn == 31 && a->rm == 31 && (a->else_inc ^ a->else_inv)) {
/* CSET & CSETM. */
- if (else_inv) {
+ if (a->else_inv) {
tcg_gen_negsetcond_i64(tcg_invert_cond(c.cond),
tcg_rd, c.value, zero);
} else {
@@ -8211,53 +8189,23 @@ static void disas_cond_select(DisasContext *s, uint32_t
insn)
tcg_rd, c.value, zero);
}
} else {
- TCGv_i64 t_true = cpu_reg(s, rn);
- TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
- if (else_inv && else_inc) {
+ TCGv_i64 t_true = cpu_reg(s, a->rn);
+ TCGv_i64 t_false = read_cpu_reg(s, a->rm, 1);
+
+ if (a->else_inv && a->else_inc) {
tcg_gen_neg_i64(t_false, t_false);
- } else if (else_inv) {
+ } else if (a->else_inv) {
tcg_gen_not_i64(t_false, t_false);
- } else if (else_inc) {
+ } else if (a->else_inc) {
tcg_gen_addi_i64(t_false, t_false, 1);
}
tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
}
- if (!sf) {
+ if (!a->sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
-}
-
-/*
- * Data processing - register
- * 31 30 29 28 25 21 20 16 10 0
- * +--+---+--+---+-------+-----+-------+-------+---------+
- * | |op0| |op1| 1 0 1 | op2 | | op3 | |
- * +--+---+--+---+-------+-----+-------+-------+---------+
- */
-static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
-{
- int op1 = extract32(insn, 28, 1);
- int op2 = extract32(insn, 21, 4);
-
- if (!op1) {
- goto do_unallocated;
- }
-
- switch (op2) {
- case 0x4: /* Conditional select */
- disas_cond_select(s, insn);
- break;
-
- default:
- do_unallocated:
- case 0x0:
- case 0x2: /* Conditional compare */
- case 0x6: /* Data-processing */
- case 0x8 ... 0xf: /* (3 source) */
- unallocated_encoding(s);
- break;
- }
+ return true;
}
static void handle_fp_compare(DisasContext *s, int size,
@@ -11212,10 +11160,6 @@ static bool btype_destination_ok(uint32_t insn, bool
bt, int btype)
static void disas_a64_legacy(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 25, 4)) {
- case 0x5:
- case 0xd: /* Data processing - register */
- disas_data_proc_reg(s, insn);
- break;
case 0x7:
case 0xf: /* Data processing - SIMD and floating point */
disas_data_proc_simd_fp(s, insn);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index a9d7d57199..5670846768 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -766,6 +766,9 @@ SETF16 0 01 11010000 00000 010010 rn:5 01101
CCMP sf:1 op:1 1 11010010 y:5 cond:4 imm:1 0 rn:5 0 nzcv:4
# Conditional select
+
+CSEL sf:1 else_inv:1 011010100 rm:5 cond:4 0 else_inc:1 rn:5 rd:5
+
# Data Processing (3-source)
&rrrr rd rn rm ra
--
2.43.0
