On Mon, Nov 04 2024, Eric Auger <eric.au...@redhat.com> wrote: > Hi Daniel, > > On 10/28/24 18:04, Daniel P. Berrangé wrote: >> On Mon, Oct 28, 2024 at 04:48:18PM +0000, Peter Maydell wrote: >>> On Mon, 28 Oct 2024 at 16:35, Daniel P. Berrangé <berra...@redhat.com> >>> wrote: >>>> On Mon, Oct 28, 2024 at 04:16:31PM +0000, Peter Maydell wrote: >>>>> On Fri, 25 Oct 2024 at 14:24, Daniel P. Berrangé <berra...@redhat.com> >>>>> wrote: >>>>>> On Fri, Oct 25, 2024 at 03:18:25PM +0200, Eric Auger wrote: >>>>>>> On 10/25/24 15:06, Daniel P. Berrangé wrote: >>>>>>>> Also, is this naming convention really the same one that users >>>>>>>> will see when they look at /proc/cpuinfo to view features ? It >>>>>>> No it is not. I do agree that the custom cpu model is very low level. It >>>>>>> is very well suited to test all series turning ID regs as writable but >>>>>>> this would require an extra layer that adapts /proc/cpuinfo feature >>>>>>> level to this regid/field abstraction. >>>>>>> >>>>>>> In /cpu/proc you will see somethink like: >>>>>>> Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp >>>>>>> asimdhp cpuid asimdrdm lrcpc dcpop asimddp >>>>>> Right, IMHO, this is the terminology that QEMU must use in user >>>>>> facing APIs. >>>>> /proc/cpuinfo's naming is rather weird for historical >>>>> reasons (for instance there is only one FEAT_FP16 feature >>>>> but cpuinfo lists "fphp" and "asimdhp" separately). >>>> There's plenty of wierd history in x86 too. In this >>>> case I might suggest just picking one of the two >>>> common names, and ignoring the other. >>>> >>>> If we really wanted to, we could alias the 2nd name >>>> to the first, but its likely not worth the bother. >>> Or we could use the standard set of architectural >>> feature names, and not have the problem at all, and not >>> have to document what we mean by our nonstandard names. >>> (cpuinfo names do actually mostly line up with the >>> standard names, just not 100%. Similarly gcc/clang command >>> line options are mostly the architectural feature name.) >> Ah, right, yes. Sorry I mis-understood you originally to be suggesting >> the same low level names as this patch. > If my understanding is correct, Peter suggested to rely on the > terminology used in > > https://developer.arm.com/documentation/109697/2024_09 > > the doc pointed to by Oliver. > > So I think the next step is to understand how those "high level" features do > map onto low level ID register field values. I think a high level feature can > map onto separate fields in separate ID regs. This may not be the most common > case though.
I went through all the FEAT_xxx features defined so far and tried to categorize them (probably with some errors here and there, but the general trend should be correct.) There's 335 features defined at the moment. Of these, the majority (295 by my count) map to one or more values in one or more id registers. These are what I'd consider the "easy" ones (added complexity if we deal with serveral values, but in general, it is clear how to handle them, and most of them actually map to a single value.) Of course, dependencies may be on top of that. Then, we have some features (~25 or so) that are actually defined by dependencies (i.e. FEAT_FOO and FEAT_BAR mean that we have FEAT_BAZ, sometimes with an architecture extension dependency thrown in as well.) These features are not really relevant when we compare two cpus since they do not map to registers directly, but they are relevant if we allow them to be specified (and use them as a kind of shorthand.) IOW, we'd need to think about how we'd handle them for comparisons and baselining. Next, let's talk about architecture extensions. All features have a level where they have been introduced as optional, some have an upper limit (e.g. FEAT_AA32EL1 is not allowed from v9.0 onwards), and quite a number of them (~65 or so) become mandatory with a certain architecture extension. Sometimes, FEAT_FOO + arch ext also implies FEAT_BAR. If we introduce Armvx.y named models, we'd need to enforce that some features are (not) set for a certain model. Complex, but not a showstopper. (We'd also need to deal with that if we worked on the register level.) We also have some registers like MIDR/REVIDR that do not correlate with any FEAT_xxx, but that we still need to handle; I would suggest to deal with them via separate cpu properties (e.g. specify a list of possible MIDR/REVIDR pairs.) I hope that there are not too many of them, although we do have some impdef registers. That leaves some headscratchers (at least for me.) E.g. FEAT_UINJ, which is optional from v9.5, and mandatory from v9.6, but where I'm unsure how we'd discover it, especially as we do not have a way to discover the architecture extensions. Maybe this will work for named actual cpus only? I'm also not sure if I understand FEAT_CHK, which is listed as optional from v8.0 and mandatory from v9.4, but every aarch64 cpu is supposed to be compliant, because CHKFEAT might be a NOP (and this is only supposed to check for FEAT_GCS? Yes, I'm confused.) So tl;dr, we cover a lot of the ID register space via FEAT_xxx (with varying complexity), but we already know about some exceptions. For some FEAT_xxx, I'm not sure if we want to handle them at all. (I also seem to remember that there some things like perf counters that don't map to any on/off features, but no idea about the details here.)
