05.11.2024 01:57, Alistair Francis wrote:
RISC-V PR for 9.2
* Fix an access to VXSAT
* Expose RV32 cpu to RV64 QEMU
* Don't clear PLIC pending bits on IRQ lowering
* Make PLIC zeroth priority register read-only
* Set vtype.vill on CPU reset
* Check and update APLIC pending when write sourcecfg
* Avoid dropping charecters with HTIF
* Apply FIFO backpressure to guests using SiFive UART
* Support for control flow integrity extensions
* Support for the IOMMU with the virt machine
* set 'aia_mode' to default in error path
* clarify how 'riscv-aia' default works
Is there anything in there which is worth picking up for qemu-stable?
Sorry, I forgot to CC the patches
I think these are all worth backporting, but aren't critical fixes so
if there are any issues applying them just skip them:
target/riscv/csr.c: Fix an access to VXSAT
hw/intc: Don't clear pending bits on IRQ lowering
target/riscv: Set vtype.vill on CPU reset
hw/intc/riscv_aplic: Check and update pending when write sourcecfg
target/riscv/kvm: set 'aia_mode' to default in error path
target/riscv/kvm: clarify how 'riscv-aia' default works
target/riscv: Fix vcompress with rvv_ta_all_1s
So I picked up all the above for 9.1.x & 9.0.x.
For 2ae6cca1d33898 "hw/intc/riscv_aplic: Check and update pending when
write sourcecfg", for 8.2.x and 7.2.x, an additional patch were needed,
0678e9f29c2301 "hw/intc/riscv_aplic: Fix in_clrip[x] read emulation"
(both applies cleanly) - hopefully this one is also okay, though it is
a bit old(ish) already.
And the aia changes are not relevant for 7.2.x.
I'm now running tests, but it looks like the whole thing is quite good
now.
Does it look ok?
I pushed current staging-7.2, staging-8.2, staging-9.0 and staging-9.1
branches to https://gitlab.com/mjt0k/qemu.git/
Thank you for the comments!
BTW, tangtiancheng....@alibaba-inc.com bounces: host
mx1.alibaba-inc.com[47.246.137.48]
said: 553 "RCPT TO" mailbox unavailable (in reply to RCPT TO command)
/mjt
