On Mon, 28 Oct 2024 at 16:20, Cornelia Huck <coh...@redhat.com> wrote: > On Fri, Oct 25 2024, Kashyap Chamarthy <kcham...@redhat.com> wrote: > > (b) The current CPU features doc[2] for Arm doesn't mention "host > > passthrough" at all. It is only implied by the last part of this > > paragraph, from the section titled "A note about CPU models and > > KVM"[3]: > > > > "Named CPU models generally do not work with KVM. There are a few > > cases that do work [...] but mostly if KVM is enabled the 'host' > > CPU type must be used." > > > > Related: in your reply[4] to Dan in this series, you write: "Having > > named models is the next thing". So named CPU models will be a > > thing in Arm, too? Then the above statement in the Arm > > 'cpu-features' will need updating :-) > > The currently existing named models are for cpus like cortex-a57; you > can use them for KVM if you happen to run on a matching host cpu, but > they only really make sense for use with tcg.
Note that those are a relic of an old and quickly abandoned design direction in KVM for Arm, where the idea was that userspace would specify the target CPU via a KVM_ARM_TARGET_* constant (initially only permitted on the matching host CPU but with some vague idea that eventually KVM would emulate the specified CPU type on different host CPUs also) On the QEMU side we feed the KVM_ARM_TARGET_* through for the two CPU models we support in TCG which also have a KVM_ARM_TARGET_* constant, which is to say Cortex-A57 and Cortex-A53. But none of the other named CPU models QEMU supports for TCG have that kind of constant. Presumably now that KVM supports "pass the guest ID regs that don't match the host" we would want to support our existing TCG-modelled named CPU types (for which we already know the ID register values, for TCG) by telling the kernel what the ID register values are. thanks -- PMM
