This series is an initial incomplete attempt at adding support for the
FEAT_XS feature in aarch64 TCG. This feature was introduced in ARMv8.7:
it adds a new memory attribute XS which indicates that a memory access
could take longer than usual to complete and also adds instruction
variants for TLBI maintenance and DSB.
These variants are implemented as no-ops, since QEMU TCG doesn't
implement caching.
This is my first foray into TCG and certain things weren't clear to me:
1. How to make sure the feature is implemented properly. Since we model
cache maintenance as no-ops my understanding is the only
functionality we need to provide is to expose the FEAT_XS feature bit
and also make sure the nXS variants trap properly if configured with
fine-grained traps.
2. Is there a point in adding a TCG test? If I read the manual
correctly, the nXS variants should trap to the undefined instruction
vector if unimplemented.
These patches lack support for FGT for now.
Signed-off-by: Manos Pitsidianakis <manos.pitsidiana...@linaro.org>
---
Manos Pitsidianakis (4):
arm: Add FEAT_XS's TLBI NXS variants
arm/tcg: add decodetree entry for DSB nXS variant
arm/tcg/cpu64: add FEAT_XS feat in max cpu
tests/tcg/aarch64: add system test for FEAT_XS
target/arm/cpu-features.h | 5 +
target/arm/helper.c | 366 +++++++++++++++++++++----------------
target/arm/tcg/a64.decode | 3 +
target/arm/tcg/cpu64.c | 1 +
target/arm/tcg/translate-a64.c | 6 +
tests/tcg/aarch64/system/feat-xs.c | 27 +++
6 files changed, 255 insertions(+), 153 deletions(-)
---
base-commit: 7e3b6d8063f245d27eecce5aabe624b5785f2a77
change-id: 20240919-arm-feat-xs-73eedb23d937
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