From: TANG Tiancheng <tangtiancheng....@alibaba-inc.com> This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets.
v4: 1. Move the implementation of roti/s/v_vec from tcg_expand_vec_op to tcg_out_vec_op, not just shi_vec. 2. Put shi and shs/v in the same patch. 3. Put load/store and vset in the same patch. 4. Change riscv_vlenb to riscv_lg2_vlenb and simplify the probe. 5. Provide stubs for the required functions and merge the functions' usage and definitions into one patch. 6. Replace riscv_host_vtype with riscv_cur_vsew and riscv_cur_type, and improve the setting of vtype. 7. Call separate functions(tcg_out_vec_ldst and tcg_out_ldst) in tcg_out_ld and tcg_out_st. 8. Optimize dupi_vec for cases where arg = 0 and arg = -1. 9. Use tcg_out_cmpsel instead of the switch statement. 10. Ensure that every single patch can compile. 11. Remove "tcg/op-gvec: Fix iteration step in 32-bit operation" as it has been incorporated into "tcg: Improve support for cmpsel_vec" (https://lists.gnu.org/archive/html/qemu-devel/2024-09/msg01281.html). This patch set depends on that patch set. v3: https://lists.gnu.org/archive/html/qemu-riscv/2024-09/msg00060.html v2: https://lists.gnu.org/archive/html/qemu-riscv/2024-08/msg00679.html v1: https://lists.gnu.org/archive/html/qemu-riscv/2024-08/msg00205.html Swung0x48 (1): tcg/riscv: Add basic support for vector TANG Tiancheng (11): util: Add RISC-V vector extension probe in cpuinfo tcg/riscv: Add vset{i}vli and ld/st vec ops tcg/riscv: Implement vector mov/dup{m/i} tcg/riscv: Add support for basic vector opcodes tcg/riscv: Implement vector cmp/cmpsel ops tcg/riscv: Implement vector neg ops tcg/riscv: Implement vector sat/mul ops tcg/riscv: Implement vector min/max ops tcg/riscv: Implement vector shi/s/v ops tcg/riscv: Implement vector roti/v/x ops tcg/riscv: Enable native vector support for TCG host host/include/riscv/host/cpuinfo.h | 2 + include/tcg/tcg.h | 7 + tcg/riscv/tcg-target-con-set.h | 7 + tcg/riscv/tcg-target-con-str.h | 3 + tcg/riscv/tcg-target.c.inc | 950 +++++++++++++++++++++++++++--- tcg/riscv/tcg-target.h | 80 +-- tcg/riscv/tcg-target.opc.h | 12 + util/cpuinfo-riscv.c | 24 +- 8 files changed, 966 insertions(+), 119 deletions(-) create mode 100644 tcg/riscv/tcg-target.opc.h -- 2.43.0
