Ping.
Jason Chien <jason.ch...@sifive.com> 於 2024年3月28日 週四 上午10:24寫道：
> In current implementation, the gdbstub allows reading vector registers
> only if V extension is supported. However, all vector extensions and
> vector crypto extensions have the vector registers and they all depend
> on Zve32x. The gdbstub should check for Zve32x instead.
>
> Signed-off-by: Jason Chien <jason.ch...@sifive.com>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Max Chou <max.c...@sifive.com>
> ---
> target/riscv/gdbstub.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index be7a02cd90..d0cc5762c2 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -338,7 +338,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState
> *cs)
>
> gdb_find_static_feature("riscv-32bit-fpu.xml"),
> 0);
> }
> - if (env->misa_ext & RVV) {
> + if (cpu->cfg.ext_zve32x) {
> gdb_register_coprocessor(cs, riscv_gdb_get_vector,
> riscv_gdb_set_vector,
> ricsv_gen_dynamic_vector_feature(cs,
> cs->gdb_num_regs),
> --
> 2.43.2
>
>
