Ping. Jason Chien <jason.ch...@sifive.com> 於 2024年3月28日 週四 上午10:23寫道：
> This patch series adds the support for Zve32x and Zvx64x and makes vector > registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. > > v2: > Rebase onto riscv-to-apply.next (commit 385e575). > v3: > Spuash patch 2 into patch 1. > Spuash patch 4 into patch 3. > > Jason Chien (3): > target/riscv: Add support for Zve32x extension > target/riscv: Add support for Zve64x extension > target/riscv: Relax vector register check in RISCV gdbstub > > target/riscv/cpu.c | 4 +++ > target/riscv/cpu_cfg.h | 2 ++ > target/riscv/cpu_helper.c | 2 +- > target/riscv/csr.c | 2 +- > target/riscv/gdbstub.c | 2 +- > target/riscv/insn_trans/trans_rvv.c.inc | 4 +-- > target/riscv/tcg/tcg-cpu.c | 33 ++++++++++++++----------- > 7 files changed, 30 insertions(+), 19 deletions(-) > > -- > 2.43.2 > >
