On Wed, 20 Mar 2024 at 20:21, Felipe Balbi <ba...@kernel.org> wrote:
>
> Minimal support with USARTs and SPIs working. This SoC will be used to
> create and nucleo-g071rb board.
>
> Signed-off-by: Felipe Balbi <ba...@kernel.org>
> ---
>
> Changes since v1:
> - Convert tabs to spaces (checkpatch.pl)
> - Correct lines longer than 80 characters (checkpatch.pl)
> - Correct num-prio-bits (Samuel Tardieu)
> - Correct num-irqs (Found reviewing RM0444)
> +static void stm32g000_soc_initfn(Object *obj)
> +{
> + STM32G000State *s = STM32G000_SOC(obj);
> + int i;
> +
> + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
> +
> + for (i = 0; i < STM_NUM_USARTS; i++) {
> + object_initialize_child(obj, "usart[*]", &s->usart[i],
> + TYPE_STM32F2XX_USART);
> + }
> +
I was just prompted by another patchset on my review queue
to look a bit more carefully at the USART section of the
datasheet, and I think that TYPE_STM32F2XX_USART is not
the correct UART type for this SoC. That UART type has its
registers in the order SR, DR, BRR, CR1, CR2, CR3, GTPR.
The G0x0 SoC describes a UART with more registers, in a
different order (CR1, CR2, CR3, BRR, GTPR, RTOR, RQR,
ISR, ICR, RDR, TDR, PRESC). That's more like the device
that this patchset adds:
https://patchew.org/QEMU/20240317103918.44375-1-arnaud.min...@telecom-paris.fr/
though I haven't tried to cross-check all these reference
manuals to see if it is identical or merely quite close...
thanks
-- PMM
