For MIPS 4KEcR1 enabling of interrupts (C0 status) no longer worked.
The patch adds the missing declaration which fixes this behaviour.
Stefan
Thiemo Seufer schrieb:
> CVSROOT: /sources/qemu
> Module name: qemu
> Changes by: Thiemo Seufer <ths> 07/05/07 13:55:33
>
> Modified files:
> . : Changelog gdbstub.c
> target-mips : TODO cpu.h exec.h fop_template.c helper.c op.c
> op_mem.c translate.c translate_init.c
>
> Log message:
> MIPS 64-bit FPU support, plus some collateral bugfixes in the
> conditional branch handling.
Index: target-mips/translate_init.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v
retrieving revision 1.7
diff -u -b -B -r1.7 translate_init.c
--- target-mips/translate_init.c 7 May 2007 13:55:33 -0000 1.7
+++ target-mips/translate_init.c 10 May 2007 18:06:35 -0000
@@ -98,6 +98,7 @@
.CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
+ .Status_rw_bitmask = 0x3278FF17,
},
{
.name = "4KEc",
