On 2024/2/22 5:22, Richard Henderson wrote:
> On 2/21/24 03:08, Jinjie Ruan via wrote:
>> Enable FEAT_NMI on the 'max' CPU.
>>
>> Signed-off-by: Jinjie Ruan <ruanjin...@huawei.com>
>> ---
>> docs/system/arm/emulation.rst | 1 +
>> target/arm/tcg/cpu64.c | 1 +
>> 2 files changed, 2 insertions(+)
>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
>
> However, this patch must be sorted last, after all support for FEAT_NMI
> is present.
Good suggestion! Placed it last is more reasonable.
>
>
> r~
>
>>
>> diff --git a/docs/system/arm/emulation.rst
>> b/docs/system/arm/emulation.rst
>> index f67aea2d83..91baf7ad69 100644
>> --- a/docs/system/arm/emulation.rst
>> +++ b/docs/system/arm/emulation.rst
>> @@ -63,6 +63,7 @@ the following architecture extensions:
>> - FEAT_MTE (Memory Tagging Extension)
>> - FEAT_MTE2 (Memory Tagging Extension)
>> - FEAT_MTE3 (MTE Asymmetric Fault Handling)
>> +- FEAT_NMI (Non-maskable Interrupt)
>> - FEAT_NV (Nested Virtualization)
>> - FEAT_NV2 (Enhanced nested virtualization support)
>> - FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED
>> algorithm)
>> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
>> index 5fba2c0f04..60f0dcd799 100644
>> --- a/target/arm/tcg/cpu64.c
>> +++ b/target/arm/tcg/cpu64.c
>> @@ -1175,6 +1175,7 @@ void aarch64_max_tcg_initfn(Object *obj)
>> t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 +
>> FEAT_DoubleFault */
>> t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
>> t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
>> + t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
>> cpu->isar.id_aa64pfr1 = t;
>> t = cpu->isar.id_aa64mmfr0;
>
