On 2/19/24 18:14, Corey Minyard wrote:
On Mon, Feb 19, 2024 at 04:53:47PM +0000, Paz Offer wrote:
Thank you very much Corey,
I am simulating an external module that wants to communicate with the board
management controller (BMC).
The real device will be connected to the board using i2c bus, and could
initiate communication at any time, by sending bytes over the bus.
And you have a simulated BMC that can do this? Or is the system running
in qemu the BMC.
I am not sure whether the 'Master-side' (the side the initiating communication)
needs to simulate a full i2c-master device, or whether my code could 'simply'
write directly to the appropriate registers of the guest OS.
Are there some examples or documentation on how to implement something like
this?
The aspeed i2c controller is capable of having another bus master on an
I2C but, but it is the only host that can currently do it.
It is doable, the code is ther for multiple bus masters, but there is no
device currently that does it. I assume that is coming at some point,
but no documentation exists on how to do it.
You can look at the git commits in hw/i2c around 37fa5ca42623 "hw/i2c:
support multiple masters" for the changes that were done to support
this.
There is an i2c-echo device implementing an I2C slave and a test,
test_arm_ast2600_evb_buildroot in tests/avocado/ machine_aspeed.py,
using it on the ast2600-evb.
Thanks,
C.
