On Sat, Feb 3, 2024 at 1:24 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> From: Andrew Jones <ajo...@ventanamicro.com>
>
> Named features are extensions which don't make sense for users to
> control and are therefore not exposed on the command line. However,
> svade is an extension which makes sense for users to control, so treat
> it like a "normal" extension. The default is false, even for the max
> cpu type, since QEMU has always implemented hardware A/D PTE bit
> updating, so users must opt into svade (or get it from a CPU type
> which enables it by default).
>
> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Signed-off-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 9 ++-------
> target/riscv/tcg/tcg-cpu.c | 6 ++++++
> 2 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 50ac7845a8..f036b153a1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1422,6 +1422,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>
> MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
> MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
> + MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
> MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
> @@ -1534,7 +1535,6 @@ const RISCVCPUMultiExtConfig
> riscv_cpu_experimental_exts[] = {
> * and priv_ver like regular extensions.
> */
> const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
> - MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
> MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>
> /*
> @@ -2182,8 +2182,6 @@ static RISCVCPUProfile RVA22U64 = {
> * Other named features that we already implement: Sstvecd, Sstvala,
> * Sscounterenw
> *
> - * Named features that we need to enable: svade
> - *
> * The remaining features/extensions comes from RVA22U64.
> */
> static RISCVCPUProfile RVA22S64 = {
> @@ -2195,10 +2193,7 @@ static RISCVCPUProfile RVA22S64 = {
> .ext_offsets = {
> /* rva22s64 exts */
> CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
> - CPU_CFG_OFFSET(ext_svinval),
> -
> - /* rva22s64 named features */
> - CPU_CFG_OFFSET(ext_svade),
> + CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
>
> RISCV_PROFILE_EXT_LIST_END
> }
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 43c32b4a15..9fc64979f1 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1314,6 +1314,12 @@ static void riscv_init_max_cpu_extensions(Object *obj)
> isa_ext_update_enabled(cpu, prop->offset, true);
> }
>
> + /*
> + * Some extensions can't be added without backward compatibilty concerns.
> + * Disable those, the user can still opt in to them on the command line.
> + */
> + cpu->cfg.ext_svade = false;
> +
> /* set vector version */
> env->vext_ver = VEXT_VERSION_1_00_0;
>
> --
> 2.43.0
>
>
