On Fri, Jan 12, 2024 at 01:15:27PM +0000, Mark Cave-Ayland wrote:
> The am53c974/dc390 PCI interrupt has two separate sources: the first is from
> the
> internal ESP device, and the second is from the PCI DMA transfer logic.
>
> Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT rather than
> driving the PCI IRQ directly, and introduce a new esp_pci_update_irq()
> function
> to generate the correct PCI IRQ level. In particular this fixes spurious
> interrupts
> being generated by setting DMA_STAT_DONE at the end of a transfer if
> DMA_CMD_INTE_D
> isn't set in the DMA_CMD register.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Guenter Roeck <li...@roeck-us.net>
Tested-by: Guenter Roeck <li...@roeck-us.net>
> ---
> hw/scsi/esp-pci.c | 32 +++++++++++++++++++++++++++-----
> 1 file changed, 27 insertions(+), 5 deletions(-)
>
> diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
> index 7117725371..15dc3c004d 100644
> --- a/hw/scsi/esp-pci.c
> +++ b/hw/scsi/esp-pci.c
> @@ -77,6 +77,29 @@ struct PCIESPState {
> ESPState esp;
> };
>
> +static void esp_pci_update_irq(PCIESPState *pci)
> +{
> + int scsi_level = !!(pci->dma_regs[DMA_STAT] & DMA_STAT_SCSIINT);
> + int dma_level = (pci->dma_regs[DMA_CMD] & DMA_CMD_INTE_D) ?
> + !!(pci->dma_regs[DMA_STAT] & DMA_STAT_DONE) : 0;
> + int level = scsi_level || dma_level;
> +
> + pci_set_irq(PCI_DEVICE(pci), level);
> +}
> +
> +static void esp_irq_handler(void *opaque, int irq_num, int level)
> +{
> + PCIESPState *pci = PCI_ESP(opaque);
> +
> + if (level) {
> + pci->dma_regs[DMA_STAT] |= DMA_STAT_SCSIINT;
> + } else {
> + pci->dma_regs[DMA_STAT] &= ~DMA_STAT_SCSIINT;
> + }
> +
> + esp_pci_update_irq(pci);
> +}
> +
> static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
> {
> ESPState *s = &pci->esp;
> @@ -151,6 +174,7 @@ static void esp_pci_dma_write(PCIESPState *pci, uint32_t
> saddr, uint32_t val)
> /* clear some bits on write */
> uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
> pci->dma_regs[DMA_STAT] &= ~(val & mask);
> + esp_pci_update_irq(pci);
> }
> break;
> default:
> @@ -161,17 +185,14 @@ static void esp_pci_dma_write(PCIESPState *pci,
> uint32_t saddr, uint32_t val)
>
> static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
> {
> - ESPState *s = &pci->esp;
> uint32_t val;
>
> val = pci->dma_regs[saddr];
> if (saddr == DMA_STAT) {
> - if (s->rregs[ESP_RSTAT] & STAT_INT) {
> - val |= DMA_STAT_SCSIINT;
> - }
> if (!(pci->sbac & SBAC_STATUS)) {
> pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
> DMA_STAT_DONE);
> + esp_pci_update_irq(pci);
> }
> }
>
> @@ -350,6 +371,7 @@ static void esp_pci_command_complete(SCSIRequest *req,
> size_t resid)
> esp_command_complete(req, resid);
> pci->dma_regs[DMA_WBC] = 0;
> pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
> + esp_pci_update_irq(pci);
> }
>
> static const struct SCSIBusInfo esp_pci_scsi_info = {
> @@ -386,7 +408,7 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error
> **errp)
> "esp-io", 0x80);
>
> pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
> - s->irq = pci_allocate_irq(dev);
> + s->irq = qemu_allocate_irq(esp_irq_handler, pci, 0);
>
> scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info);
> }
> --
> 2.39.2
>
