On Mon, Dec 18, 2023 at 11:00 PM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> The RVA22S64 profile consists of the following:
>
> - all mandatory extensions of RVA22U64;
> - priv spec v1.12.0;
> - satp mode sv39;
> - Ssccptr, a cache related named feature that we're assuming always
> enable since we don't implement a cache;
> - Other named features already implemented: Sstvecd, Sstvala,
> Sscounterenw;
> - the new Svade named feature that was recently added.
>
> Most of the work is already done, so this patch is enough to implement
> the profile.
>
> After this patch, the 'rva22s64' user flag alone can be used with the
> rva64i CPU to boot Linux:
>
> -cpu rv64i,rva22s64=true
>
> This is the /proc/cpuinfo with this profile enabled:
>
> # cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa :
> rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt
> mmu : sv39
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index aa33e7a1cf..f57a9ee298 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1560,8 +1560,40 @@ static RISCVCPUProfile RVA22U64 = {
> }
> };
>
> +/*
> + * As with RVA22U64, RVA22S64 also defines 'named features'.
> + *
> + * Cache related features that we consider enabled since we don't
> + * implement cache: Ssccptr
> + *
> + * Other named features that we already implement: Sstvecd, Sstvala,
> + * Sscounterenw
> + *
> + * Named features that we need to enable: svade
> + *
> + * The remaining features/extensions comes from RVA22U64.
> + */
> +static RISCVCPUProfile RVA22S64 = {
> + .parent = &RVA22U64,
> + .name = "rva22s64",
> + .misa_ext = RVS,
> + .priv_spec = PRIV_VERSION_1_12_0,
> + .satp_mode = VM_1_10_SV39,
> + .ext_offsets = {
> + /* rva22s64 exts */
> + CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
> + CPU_CFG_OFFSET(ext_svinval),
> +
> + /* rva22s64 named features */
> + CPU_CFG_OFFSET(svade),
> +
> + RISCV_PROFILE_EXT_LIST_END
> + }
> +};
> +
> RISCVCPUProfile *riscv_profiles[] = {
> &RVA22U64,
> + &RVA22S64,
> NULL,
> };
>
> --
> 2.43.0
>
>
